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1. 发明授权

US09391621B2 Configurable multiply-accumulate 有权
标题翻译：可配置乘法累加
公开(公告)号：US09391621B2
公开(公告)日：2016-07-12
申请号：US14102300
申请日：2013-12-10
申请人： Scaleo Chip
发明人： Loic Vezier , Farid Tahiri
IPC分类号： G06F7/38 , H03K19/177 , G06F7/544
CPC分类号： H03K19/17732 , G06F7/5443
摘要： Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.
摘要翻译：现场可编程门阵列（FPGA）除随机逻辑外，还包含可配置于随机逻辑的其他组件，例如处理单元，乘法累加（MAC）单元，模拟电路和其他元件，以增强 FPGA的功能。提供用于现场可配置MAC单元的电路以允许ADD，SUBTRACT，MULTIPLY和SHIFT功能的各种配置。可选地，注册输入和注册输出支持多循环路径。常数的配置有助于电路的配置，以在硬件中执行无限脉冲响应（IIR）和有限脉冲响应（FIR）功能。

2. 发明授权

US09632139B2 IO pad circuitry with safety monitoring and control for integrated circuits 有权
公开(公告)号：US09632139B2
公开(公告)日：2017-04-25
申请号：US14050077
申请日：2013-10-09
申请人： Scaleo Chip
发明人： Cédric Chillie , Tatiana Kauric
IPC分类号： G01R31/317 , H04L1/00 , G06F11/07 , G01R31/3187
CPC分类号： G01R31/31715 , G01R31/31713 , G01R31/3187 , G06F11/07 , H04L1/00
摘要： An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

3. 发明授权

US09077339B2 Robust flexible logic unit 有权
标题翻译：强大的灵活逻辑单元
公开(公告)号：US09077339B2
公开(公告)日：2015-07-07
申请号：US14321458
申请日：2014-07-01
申请人： Scaleo Chip
发明人： Farid Tahiri , Pierre Dominique Xavier Garaccio
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/17764
摘要： A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration.
摘要翻译：强大的灵活逻辑单元（FLU）主要是将其作为嵌入式现场可编程门阵列（EFPGA）而非排他性使用。该单元由排列成列和列的瓦片的阵列的多个可编程构建块瓦片组成，并且通过使用锁定器来编程，所述锁存器使用锁定器被顺序地编程和锁定锁定位作为提供的位流的一部分。奇数和偶数时钟的方案防止锁存透明度，并确保一旦数据到达目的地，它被正确锁定，不会被无意地覆盖。强大的FLU进一步配备了循环冗余检查功能，以提供故障列配置的指示。

4. 发明申请

US20150091614A1 Robust Flexible Logic Unit 有权
标题翻译：强大的灵活逻辑单元
公开(公告)号：US20150091614A1
公开(公告)日：2015-04-02
申请号：US14321458
申请日：2014-07-01
申请人： Scaleo Chip
发明人： Farid Tahiri , Pierre Dominique Xavier Garaccio
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17764
摘要： A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration.
摘要翻译：强大的灵活逻辑单元（FLU）主要是将其作为嵌入式现场可编程门阵列（EFPGA）而非排他性使用。该单元由排列成列和列的瓦片的阵列的多个可编程构建块瓦片组成，并且通过使用锁定器来编程，所述锁存器使用锁定器被顺序地编程和锁定锁定位作为提供的位流的一部分。奇数和偶数时钟的方案防止锁存透明度，并确保一旦数据到达目的地，它被正确锁定，不会被无意地覆盖。强大的FLU进一步配备了循环冗余检查功能，以提供故障列配置的指示。

5. 发明申请

US20140365814A1 IO Pad Circuitry with Safety Monitoring and Control for Integrated Circuits 有权
标题翻译：具有安全监控和集成电路控制的IO Pad电路
公开(公告)号：US20140365814A1
公开(公告)日：2014-12-11
申请号：US14050077
申请日：2013-10-09
申请人： Scaleo Chip
发明人： Cédric Chillie , Tatiana Kauric
IPC分类号： G06F11/07
CPC分类号： G01R31/31715 , G01R31/31713 , G01R31/3187 , G06F11/07 , H04L1/00
摘要： An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.
摘要翻译：用于集成电路（IC）的输入/输出（IO）焊盘电路，其配备有安全监控和控制电路，以确保向/从IO焊盘提供的信号正常运行。 IO垫电路允许监测IO焊盘信号，检测不期望的行为，例如错误的信号电平或错误的波形。此外，根据选择的安全模式，进一步实现通过覆盖所监视的信号来校正IO焊盘信号。当处于完全安全模式时，根据需要提供信号，而在部分安全模式下，仅根据状态提供某些信号。分组安全模式允许使用单个控件为一组IO垫提供安全状态。还提供了到IC垫的多个输入信号之间的监控电路。

6. 发明申请

US20150303926A1 Robust Flexible Logic Unit 有权
标题翻译：强大的灵活逻辑单元
公开(公告)号：US20150303926A1
公开(公告)日：2015-10-22
申请号：US14754162
申请日：2015-06-29
申请人： Scaleo Chip
发明人： Farid Tahiri , Pierre Dominique Xavier Garaccio
IPC分类号： H03K19/177
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/17756 , H03K19/17764
摘要： A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.
摘要翻译：强大的灵活逻辑单元（FLU）主要是将其作为嵌入式现场可编程门阵列（EFPGA）而非排他性使用。该单元由多个可编程构建块瓦片组成，其中多个可排列的列和瓦片阵列，以及通过瓦片和逐列的编程瓦片，使用使用锁定位的锁存器，锁存器使用作为提供了位流。奇数和偶数时钟的方案可防止锁定透明度，并确保加载的数据被正确锁定，以防止覆盖。强大的FLU进一步配备了循环冗余检查功能，以提供故障列配置的指示。本发明还提供了将单个FLU分离成多个独立的可重新配置的FLU部分，具有独立的用户时钟和复位，用于实现多个独立的功能或用于为关键功能建立冗余。

7. 发明授权

US09048827B2 Flexible logic unit 有权
标题翻译：灵活的逻辑单元
公开(公告)号：US09048827B2
公开(公告)日：2015-06-02
申请号：US14153760
申请日：2014-01-13
申请人： Scaleo Chip
发明人： Farid Tahiri , Pierre Dominique Xavier Garaccio
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/17764
摘要： A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten.
摘要翻译：一个灵活的逻辑单元（FLU）主要是将其作为嵌入式现场可编程门阵列（EFPGA）而非排他性的。该单元由排列成列和列的瓦片的阵列的多个可编程构建块瓦片组成，并且通过使用锁定器来编程，所述锁存器使用锁定器被顺序地编程和锁定锁定位作为提供的位流的一部分。奇数和偶数时钟的方案防止锁存透明度，并确保一旦数据到达目的地，它被正确锁定，不会被无意地覆盖。

8. 发明申请

US20150095388A1 Configurable Multiply-Accumulate 有权
标题翻译：可配置乘法累加
公开(公告)号：US20150095388A1
公开(公告)日：2015-04-02
申请号：US14102300
申请日：2013-12-10
申请人： Scaleo Chip
发明人： Loic Vezier , Farid Tahiri
IPC分类号： H03K19/177
CPC分类号： H03K19/17732 , G06F7/5443
摘要： Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.
摘要翻译：现场可编程门阵列（FPGA）除随机逻辑外，还包含可配置于随机逻辑的其他组件，例如处理单元，乘法累加（MAC）单元，模拟电路和其他元件，以增强 FPGA的功能。提供用于现场可配置MAC单元的电路以允许ADD，SUBTRACT，MULTIPLY和SHIFT功能的各种配置。可选地，注册输入和注册输出支持多循环路径。常数的配置有助于电路的配置，以在硬件中执行无限脉冲响应（IIR）和有限脉冲响应（FIR）功能。

9. 发明申请

US20150058669A1 Method and Apparatus for Error Management of an Integrated Circuit System 有权
标题翻译：集成电路系统误差管理方法与装置
公开(公告)号：US20150058669A1
公开(公告)日：2015-02-26
申请号：US14084222
申请日：2013-11-19
申请人： Scaleo Chip
发明人： Bruno Sallé
IPC分类号： G06F11/22
CPC分类号： G06F11/2236 , G06F11/0706 , G06F11/0781 , G06F11/22
摘要： An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
摘要翻译：提出了一种用于集成电路系统中的误差管理的装置和方法。错误管理单元（EMU）设备管理可能被屏蔽或未被屏蔽的关键和非关键错误。 EMU包括具有BOOT状态，CONFIG状态，FUNCT状态，WARNING状态和ERROR状态的EMU状态机。该方法公开了EMU状态机中的转换。当处于ERROR状态时，可能会应用错误反应。错误反应的目的是通过软件和硬件手段恢复错误。 EMU可以在错误状态下进一步适当地警告系统，因此用作安全机制，允许收集故障检测器单元发出的错误信号，并且可以进一步对故障单元采取行动以进行恢复。

10. 发明授权

US09658082B2 Method of determining the instantaneous angular position of a crankshaft target optimized for starting the engine 有权
公开(公告)号：US09658082B2
公开(公告)日：2017-05-23
申请号：US14660238
申请日：2015-03-17
申请人： IFP Energies nouvelles , Scaleo Chip
发明人： Thierry Lepage , Farid Tahiri
IPC分类号： G01M15/00 , G01D5/14 , F02D41/00 , F02D41/06
CPC分类号： G01D5/142 , F02D41/009 , F02D41/065 , F02D2041/0092 , F02D2041/0095 , F02D2250/06
摘要： A method for determining an absolute angular position of a crankshaft target of an internal combustion engine, including a plurality of teeth for which at least one signal is acquired representing the passage of each tooth in front of a sensor as a function of time comprising: i. generating during a phase with the engine running an absolute angular position from the at least one signal and from a period of a tooth; ii. continuously determining during a phase of stopping the engine when determination of the period is not possible, a number of teeth passing in front of the sensor; and iii. during a phase of restarting the engine, using a number of teeth to reduce the cycle synchronization time.

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