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1. 发明授权

US5019966A Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data 失效
标题翻译：当接收处理器时，使用忙信号来控制预定长度数据的传输的双处理器正在处理先前接收到的数据
公开(公告)号：US5019966A
公开(公告)日：1991-05-28
申请号：US091813
申请日：1987-09-01
申请人： Sayuri Saito , Kazutoshi Yoshizawa , Yoshitaka Kitada
发明人： Sayuri Saito , Kazutoshi Yoshizawa , Yoshitaka Kitada
IPC分类号： G06F13/42 , G06F15/17
CPC分类号： G06F13/4256 , G06F15/17
摘要： A transmitting data processor comprises a data processing unit for supplying a predetermined length of data to be transferred and generating a transfer start signal, and a data transferring unit receiving the predetermined length of data to be transferred from the data processing unit and for transferring the predetermined length of data in a serial form to a receiving data processor. The transmitting data processor also includes a busy detector for detecting a busy signal from the receiving data processor, a register for temporarily holding the transfer start signal from the data processing unit, and a start controller associated to the data transferring unit for causing the data transferring unit to stop the transfer of data during the period the busy signal is active and for allowing the data transferring unit to start the transfer of data when the busy signal becomes inactive after the transfer start signal is generated.The receiving data processor includes a data receiving unit for receiving the predetermined length of data transferred from the transmitting data processor, and a data processing unit coupled to the receiving unit for processing the received data and generating a transfer acknowledge signal when it has completed the processing of the received data. The receiving data processor also includes a busy signal generator for generating the above mentioned busy signal in response to completion of reception of the predetermined length of data and making the busy signal inactive when the transfer acknowledge signal is generated.
摘要翻译：发送数据处理器包括：数据处理单元，用于提供要传输的预定长度的数据并生成传送开始信号;以及数据传送单元，从数据处理单元接收要传送的预定长度的数据，并传送预定的以串行形式将数据长度传送到接收数据处理器。发送数据处理器还包括用于检测来自接收数据处理器的忙信号的忙检测器，用于临时保存来自数据处理单元的传送开始信号的寄存器，以及与数据传送单元相关联的启动控制器，用于使数据传送在忙信号有效期间停止数据传送的单元，并且在生成传送开始信号之后，当忙信号变为无效时允许数据传送单元开始传输数据。接收数据处理器包括数据接收单元，用于接收从发送数据处理器传送的预定长度的数据;以及数据处理单元，耦合到接收单元，用于处理接收到的数据，并在其完成处理时产生传送确认信号的接收数据。接收数据处理器还包括忙信号发生器，用于响应于接收到预定长度的数据而完成上述忙信号，并且当生成传送确认信号时使忙信号无效。

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