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1. 发明申请

US20090231008A1 FLIP-FLOP CIRCUIT THAT LATCHES INPUTTED DATA 有权
标题翻译：插入数据的FLIP-FLOP电路
公开(公告)号：US20090231008A1
公开(公告)日：2009-09-17
申请号：US12371094
申请日：2009-02-13
申请人： Satoru Sekine , Shinji Furuichi
发明人： Satoru Sekine , Shinji Furuichi
IPC分类号： H03K3/289
CPC分类号： H03K3/356139 , H03K3/012
摘要： A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.
摘要翻译：触发器电路通过幅度小于输入数据D的第一时钟信号来工作。一对晶体管分别接收输入数据D和反相输入数据* D以锁存输入数据D.激活电路在导通状态下激活该对晶体管。控制电路接收第一时钟信号，并且从接收的第一时钟信号的边沿定时开始，将激活电路设置为导通状态达预定时间段。控制电路增加第一时钟信号的幅度，并且通过使用作为具有增加的幅度的第一时钟信号的第二时钟信号将激活电路设置为导通状态。

2. 发明申请

US20050212787A1 Display apparatus that controls luminance irregularity and gradation irregularity, and method for controlling said display apparatus 审中-公开
标题翻译：控制亮度不均匀性和灰度不均匀性的显示装置，以及控制所述显示装置的方法
公开(公告)号：US20050212787A1
公开(公告)日：2005-09-29
申请号：US11084134
申请日：2005-03-21
申请人： Yukihiro Noguchi , Satoru Sekine , Kouiti Yamada , Shoichiro Matsumoto
发明人： Yukihiro Noguchi , Satoru Sekine , Kouiti Yamada , Shoichiro Matsumoto
IPC分类号： G09G3/20 , G09G3/32 , G09G5/00
CPC分类号： G09G3/3233 , G09G3/2022 , G09G3/3291 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/0218 , G09G2310/066
摘要： In an active matrix display apparatus, the drive transistor to drive an OLED self-corrects the operation timing of the drive transistor. A correction transistor controls on and off of the self-correction. The drive circuit self-corrects the operation of the drive transistor by generating a luminance signal which is corrected based on a predetermined signal delivered temporarily and an operation threshold value. The current flowing to the OLED is controlled by gradually changing the voltage of luminance signal from a ramp signal line. After the luminance signal for one frame is inputted to each pixel, the same luminance signal for one frame is inputted to the each pixel in a reversed scanning direction. One frame period is divided into a plurality of subframe periods and the data control circuit inputs respectively the same luminance signal to each pixel in the plurality of subframe periods.
摘要翻译：在有源矩阵显示装置中，用于驱动OLED的驱动晶体管自动校正驱动晶体管的操作定时。校正晶体管控制自校正的开和关。驱动电路通过产生基于临时传送的预定信号校正的亮度信号和操作阈值来自动校正驱动晶体管的操作。通过逐渐改变来自斜坡信号线的亮度信号的电压来控制流向OLED的电流。在将一帧的亮度信号输入到每个像素之后，将相同的一帧的亮度信号在相反的扫描方向上输入到每个像素。一个帧周期被分成多个子帧周期，并且数据控制电路分别向多个子帧周期中的每个像素输入相同的亮度信号。

3. 发明申请

US20080218235A1 SEMICONDUCTOR INTEGRATED CIRCUIT WITH FLIP-FLOP CIRCUITS MOUNTED THEREON 有权
标题翻译：具有FLIP-FLOP电路的半导体集成电路安装在
公开(公告)号：US20080218235A1
公开(公告)日：2008-09-11
申请号：US12044406
申请日：2008-03-07
申请人： Satoru SEKINE , Yoshitaka Ueda , Takashi Asano , Shinji Furuichi , Atsushi Wada
发明人： Satoru SEKINE , Yoshitaka Ueda , Takashi Asano , Shinji Furuichi , Atsushi Wada
IPC分类号： H03K3/356 , H03K3/00 , H03K3/037
CPC分类号： H03K3/35625
摘要： A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.
摘要翻译：具有不同电路结构的执行相同数字信号处理的多个触发电路混合在单个半导体衬底上。多个触发器电路中的第一触发器电路通过至少两级反相器接收从触发器电路外部提供的时钟信号，并且利用从反相器输出的时钟信号进行操作。第二触发器电路通过至少一个具有比包含在第一触发器电路中的反相器的级数少的级数的反相器接收从触发器电路的外部提供的时钟信号，并且以至少一个时钟信号和从逆变器输出的时钟信号。

4. 发明申请

US20060002258A1 Method and apparatus for ejecting a medium 审中-公开
标题翻译：用于喷射介质的方法和装置
公开(公告)号：US20060002258A1
公开(公告)日：2006-01-05
申请号：US11165611
申请日：2005-06-23
申请人： Takashi Nakamura , Satoru Sekine
发明人： Takashi Nakamura , Satoru Sekine
IPC分类号： G11B15/52
CPC分类号： G11B17/051 , G11B17/057 , G11B33/027 , G11B33/10 , G11B33/125
摘要： An electronic apparatus and a method for ejecting a medium are provided that can ensure identification of eject keys for media even when the display of a touch panel surface is difficult to view. In the electronic apparatus, a touch panel 50 is slid to open a plurality of medium insertion/ejection ports 61 to 63, so that the predetermined medium (CD, DVD, MD) can be inserted therein and ejected therefrom. When the medium insertion/ejection port is opened, a touch panel surface is divided into areas, and the divisional areas SAR1 to SAR3 are allocated to touch switches EJK1 to EJK3 for ejection of the respective predetermined media. When the touch panel surface is touched, it is detected which touch switch is turned on, and then the medium corresponding to the touch switch turned on is ejected.
摘要翻译：提供了一种用于弹出介质的电子设备和方法，其可以确保识别用于介质的弹出键，即使当触摸面板的显示难以观看时。在电子设备中，触摸板50滑动以打开多个介质插入/喷射口61至63，使得可以将预定介质（CD，DVD，MD）插入其中并从其中弹出。当介质插入/打开端口打开时，触摸面板表面被划分为多个区域，分区SAR 1至SAR 3被分配到触摸开关EJK 1至EJK 3以便弹出相应的预定介质。当触摸面板表面被触摸时，检测到哪个触摸开关被打开，然后弹出对应于触摸开关的介质。

5. 发明授权

US08008959B2 Flip-flop circuit that latches inputted data 有权
标题翻译：锁存输入数据的触发器电路
公开(公告)号：US08008959B2
公开(公告)日：2011-08-30
申请号：US12371094
申请日：2009-02-13
申请人： Satoru Sekine , Shinji Furuichi
发明人： Satoru Sekine , Shinji Furuichi
IPC分类号： H03K3/289
CPC分类号： H03K3/356139 , H03K3/012
摘要： A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.
摘要翻译：触发器电路通过幅度小于输入数据D的第一时钟信号来工作。一对晶体管分别接收输入数据D和反相输入数据* D以锁存输入数据D.激活电路在导通状态下激活一对晶体管。控制电路接收第一时钟信号，并且从接收的第一时钟信号的边沿定时开始，将激活电路设置为导通状态达预定时间段。控制电路增加第一时钟信号的幅度，并且通过使用作为具有增加的幅度的第一时钟信号的第二时钟信号将激活电路设置为导通状态。

6. 发明授权

US07746138B2 Semiconductor integrated circuit with flip-flop circuits mounted thereon 有权
标题翻译：具有安装在其上的触发器电路的半导体集成电路
公开(公告)号：US07746138B2
公开(公告)日：2010-06-29
申请号：US12044406
申请日：2008-03-07
申请人： Satoru Sekine , Yoshitaka Ueda , Takashi Asano , Shinji Furuichi , Atsushi Wada
发明人： Satoru Sekine , Yoshitaka Ueda , Takashi Asano , Shinji Furuichi , Atsushi Wada
IPC分类号： H03K3/00
CPC分类号： H03K3/35625
摘要： A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.
摘要翻译：具有不同电路结构的执行相同数字信号处理的多个触发电路混合在单个半导体衬底上。多个触发器电路中的第一触发器电路通过至少两级反相器接收从触发器电路外部提供的时钟信号，并且利用从反相器输出的时钟信号进行操作。第二触发器电路通过至少一个具有比包含在第一触发器电路中的反相器的级数少的级数的反相器接收从触发器电路的外部提供的时钟信号，并且以至少一个时钟信号和从逆变器输出的时钟信号。

7. 发明申请

US20080030250A1 FLIP-FLOP CIRCUIT 审中-公开
标题翻译： FLIP-FLOP电路
公开(公告)号：US20080030250A1
公开(公告)日：2008-02-07
申请号：US11693146
申请日：2007-03-29
申请人： Shinji Furuichi , Satoru Sekine
发明人： Shinji Furuichi , Satoru Sekine
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/35625 , H03K3/356034
摘要： A pair of transistors receive the input of signals of input data and the inverted input data. An activation circuit, which is provided between the pair of transistors and fixed potential, activates the pair of transistors in a conduction state. A clock control circuit receives a clock signal and sets the activation circuit to a conduction state for a predetermined period starting from an edge timing of the clock signal. The activation circuit includes a first activation transistor and a second activation transistor which are connected in cascade with each other. The clock control circuit turns on both the first activation transistor and the second transistor for the predetermined period starting from the edge timing of the clock signal, and turns off at least one of the first activation transistor and the second activation transistor for a period other than the predetermined period.
摘要翻译：一对晶体管接收输入数据和反相输入数据的信号输入。在一对晶体管和固定电位之间提供的激活电路在导通状态下激活一对晶体管。时钟控制电路从时钟信号的边沿定时接收时钟信号并将激活电路设置为导通状态一段预定时间。激活电路包括彼此级联连接的第一激活晶体管和第二激活晶体管。时钟控制电路从时钟信号的边沿定时开始第一激活晶体管和第二晶体管的预定周期，并且将第一激活晶体管和第二激活晶体管中的至少一个截止，预定期间。

8. 发明授权

US06930906B2 Ferroelectric memory and operating method therefor, and memory device 有权
标题翻译：铁电存储器及其操作方法及存储器件
公开(公告)号：US06930906B2
公开(公告)日：2005-08-16
申请号：US10387869
申请日：2003-03-14
申请人： Shigeharu Matsushita , Yoh Takano , Satoru Sekine
发明人： Shigeharu Matsushita , Yoh Takano , Satoru Sekine
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.
摘要翻译：能够提高未选择存储单元中的抗干扰性的铁电存储器包括位线，布置成与位线相交的字线以及布置在位线和字线a之间的存储单元，包括：铁电电容器和串联连接到铁电电容器的二极管。因此，当在数据写入或数据读取中向非选择单元施加难以向二极管供给电流的范围内的电压时，基本上不向铁电体电容器施加电压。

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