专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08145443B2 Fourier transform-based phasor estimation method and apparatus capable of eliminating influence of exponentially decaying DC offsets 有权
标题翻译：能够消除指数衰减DC偏移影响的基于傅立叶变换的相量估计方法和装置
公开(公告)号：US08145443B2
公开(公告)日：2012-03-27
申请号：US12423223
申请日：2009-04-14
申请人： Sang Hee Kang , Dong Gyu Lee
发明人： Sang Hee Kang , Dong Gyu Lee
IPC分类号： G01R23/16
CPC分类号： G01R19/0015 , G01R15/18 , G01R31/024
摘要： Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal.
摘要翻译：本文公开了一种能够消除指数衰减DC偏移影响的基于傅立叶变换的相量估计方法和装置。根据本发明实施例的基于傅里叶变换的相量估计方法，对输入信号进行采样，将输入信号的一周期数据的采样分成至少两个采样组。对每个样本组执行离散傅里叶变换（DFT）。基于每个样本组上的DFT的结果计算输入信号中包括的DC偏移，并且使用计算的DC偏移计算由DC偏移引起的误差。通过从输入信号的DFT的结果中消除由DC偏移引起的计算出的误差来估计包括在输入信号中的基频分量的相量。

2. 发明授权

US07602660B2 Redundancy circuit semiconductor memory device 失效
标题翻译：冗余电路半导体存储器件
公开(公告)号：US07602660B2
公开(公告)日：2009-10-13
申请号：US11773926
申请日：2007-07-05
申请人： Sang-Hee Kang
发明人： Sang-Hee Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/838 , G11C29/787
摘要： A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.
摘要翻译：半导体存储器件中的冗余电路包括：熔丝组控制器，配置为输出根据所施加的地址信号使能的冗余使能信号; 冗余选择器备用冗余选择器; 以及备用熔丝控制器，其被配置为由所述冗余启用信号控制，并且输出选择控制信号，所述选择控制信号根据内部熔丝选项选择所述冗余选择器和备用冗余选择器中的至少一个。

3. 发明授权

US07471578B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07471578B2
公开(公告)日：2008-12-30
申请号：US11739684
申请日：2007-04-24
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same. The internal voltage generation control circuit comprises a row active controller for enabling a first internal voltage generation control signal when a row active signal is enabled upon input of an active command and then disabling the first internal voltage generation control signal after the lapse of a first predetermined delay time if an RAS activation guarantee signal is enabled at a RAS active time after the first internal voltage generation control signal is enabled, an input/output controller for enabling a second internal voltage generation control signal when the row active signal and at least one of a data input signal and a data output signal are enabled and then disabling the second internal voltage generation control signal after the lapse of a second predetermined delay time if a row precharge signal is enabled or if the data input signal and data output signal are disabled, and a row precharge controller for enabling a third internal voltage generation control signal for a third predetermined delay time if the row precharge signal is enabled.
摘要翻译：这里公开了内部电压产生控制电路和使用该内部电压产生控制电路的内部电压产生电路。内部电压产生控制电路包括行有源控制器，用于当输入有效命令时使能行活动信号时能够实现第一内部电压产生控制信号，然后在经过第一预定值之后禁用第一内部电压产生控制信号如果RAS激活保证信号在第一内部电压产生控制信号被使能之后的RAS有效时间被使能的延迟时间，一个输入/输出控制器，用于当行活动信号和第二内部电压产生控制信号中的至少一个数据输入信号和数据输出信号被使能，然后如果行预充电信号被使能或数据输入信号和数据输出信号被禁止，则在经过第二预定延迟时间之后禁用第二内部电压产生控制信号，以及用于启用第三内部电压产生控制信号fo的行预充电控制器如果行预充电信号被使能，则为第三预定延迟时间。

4. 发明授权

US07282986B2 Negative voltage generator circuit 失效
标题翻译：负电压发生器电路
公开(公告)号：US07282986B2
公开(公告)日：2007-10-16
申请号：US11193814
申请日：2005-07-27
申请人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
发明人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.
摘要翻译：本发明涉及一种用于将半导体集成电路（IC）可靠地提供负电压的负电压产生电路。电荷泵送装置通过将电荷泵送到提供给第一节点和第二节点之一的预定水平来产生负电压。控制装置响应于负电压的电平，以预定间隔交替地提供按时钟交替的第一和第二泵送时钟信号。泵送控制器响应于第一和第二泵送时钟信号控制提供给第一节点和第二节点的电荷量。此外，复位控制器将电荷泵送装置的第一节点和第二节点复位为当第一和第二抽运时钟信号失活时的负电压的电平。

5. 发明授权

US07280418B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07280418B2
公开(公告)日：2007-10-09
申请号：US11469552
申请日：2006-09-01
申请人： Sang Hee Kang , Kyoung Nam Kim
发明人： Sang Hee Kang , Kyoung Nam Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/12 , G11C11/4094
摘要： An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k-1-th latch, and latches state information of the output signal of the k-1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要翻译：提供内部电压产生控制电路和使用其的内部电压产生电路。内部电压产生控制电路包括第一至第n锁存器和逻辑单元。第一锁存器作为输入信号接收在输入读/写命令之后产生的列有效脉冲信号，并且在预定时间期间锁存在启用时钟信号时接收的列活动脉冲信号的状态信息，以及然后输出锁存信息。第k个锁存器（2 <= k <= n）接收第k-1个锁存器的输出信号，并且锁存当时钟信号为时钟信号时接收到的第k-1个锁存器的输出信号的状态信息在预定时间内启用，然后输出锁存信息。逻辑单元执行列活动脉冲信号和n个锁存器的输出信号之间的逻辑运算，并输出内部电压产生控制信号。

6. 发明授权

US07257037B2 Redundancy circuit in semiconductor memory device 失效
标题翻译：半导体存储器件中的冗余电路
公开(公告)号：US07257037B2
公开(公告)日：2007-08-14
申请号：US11262105
申请日：2005-10-28
申请人： Sang-Hee Kang
发明人： Sang-Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C29/838 , G11C29/787
摘要： A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.
摘要翻译：半导体存储器件中的冗余电路包括：熔丝组控制器，配置为输出根据所施加的地址信号使能的冗余使能信号; 冗余选择器备用冗余选择器; 以及备用熔丝控制器，其被配置为由所述冗余启用信号控制，并且输出选择控制信号，所述选择控制信号根据内部熔丝选项选择所述冗余选择器和备用冗余选择器中的至少一个。

7. 发明授权

US06989703B2 Shared delay circuit of a semiconductor device 失效
标题翻译：半导体器件的共享延迟电路
公开(公告)号：US06989703B2
公开(公告)日：2006-01-24
申请号：US10673014
申请日：2003-09-26
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K5/13 , H03K5/1534 , H03K2005/00293
摘要： A shared delay circuit of a semiconductor device can share a plurality of delay elements having the same function by integrating the delay elements. The shared delay circuit includes an input signal conversion unit for converting a plurality of input signals into a plurality of pulse signals, a delay unit for delaying the pulse signals outputted from the input signal conversion unit for a predetermined time to output the delayed pulse signal, and a switch and output control unit for receiving the pulse signals outputted from the input signal conversion unit and the delayed pulse signals delayed for the predetermined time through the delay unit, and outputting the delayed pulse signals in the same form as the input signals inputted to the input signal conversion unit. According to the shared delay circuit, the repeated arrangement of circuits having the same function can be avoided by sharing the delay circuits in the semiconductor device and thus the installation area of the delay circuits can be reduced.
摘要翻译：半导体器件的共享延迟电路可以通过对延迟元件进行积分来共享具有相同功能的多个延迟元件。共享延迟电路包括：输入信号转换单元，用于将多个输入信号转换为多个脉冲信号;延迟单元，用于将输入信号转换单元输出的脉冲信号延迟预定时间，以输出延迟的脉冲信号; 以及开关输出控制单元，用于接收从输入信号转换单元输出的脉冲信号和通过延迟单元延迟预定时间的延迟脉冲信号，并以与输入的输入信号相同的形式输出延迟的脉冲信号输入信号转换单元。根据共享延迟电路，可以通过共享半导体器件中的延迟电路来避免具有相同功能的电路的重复布置，从而可以减少延迟电路的安装面积。

8. 发明授权

US06958894B2 Relaying method for protecting a transformer using a difference of current 失效
标题翻译：使用电流差异保护变压器的中继方法
公开(公告)号：US06958894B2
公开(公告)日：2005-10-25
申请号：US10333390
申请日：2001-05-17
申请人： Yong Cheol Kang , Sang Hee Kang , Byung Eun Lee , Jae Sung Yun
发明人： Yong Cheol Kang , Sang Hee Kang , Byung Eun Lee , Jae Sung Yun
IPC分类号： H02H3/40 , H02H7/045 , H02H7/04
CPC分类号： H02H7/045 , H02H3/40
摘要： Disclosed is a relaying method for protecting a transformer by using a difference of current. A decision function, related to the rate of change of a primary current, a secondary current, or a differential current, is used for determining whether a detected abnormal current is due to the inrush or internal fault.
摘要翻译：公开了一种通过使用电流差来保护变压器的中继方法。使用与初级电流，次级电流或差动电流的变化率有关的决定功能来确定检测到的异常电流是否是由于涌入或内部故障。

9. 发明授权

US06771555B2 Row access information transfer device using internal wiring of a memory cell array 失效
标题翻译：行访问信息传输设备使用存储单元阵列的内部布线
公开(公告)号：US06771555B2
公开(公告)日：2004-08-03
申请号：US10152705
申请日：2002-05-22
申请人： Sang Hee Kang
发明人： Sang Hee Kang
IPC分类号： G11C800
CPC分类号： G11C29/80
摘要： Row access information transfer devices and methods are disclosed which use an internal wiring of a memory cell array to transfer information to a column fuse box array. The disclosed techniques and structures can increase the efficiency of a circuit by transferring sense amplifier and wordline control signals relating to a specific row block corresponding to an inputted row address to a column fuse box array using wiring within the cell array, when the row block is accessed in DRAM.
摘要翻译：公开了使用存储单元阵列的内部布线将信息传送到列保险丝盒阵列的行访问信息传送设备和方法。所公开的技术和结构可以通过将读取放大器和与输入的行地址相对应的特定行块相关的字线控制信号传送到列保险丝盒阵列来增加电路的效率，使用单元阵列内的布线，当行块为在DRAM中访问

10. 发明申请

US20130201768A1 INTERNAL VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF GENERATING INTERNAL VOLTAGE 审中-公开
标题翻译：内部电压产生电路，包括其的半导体存储器件以及产生内部电压的方法
公开(公告)号：US20130201768A1
公开(公告)日：2013-08-08
申请号：US13606716
申请日：2012-09-07
申请人： Sang-Hee KANG , Jong-Eun LEE , Dong-Su LEE
发明人： Sang-Hee KANG , Jong-Eun LEE , Dong-Su LEE
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C5/147 , G05F1/56 , G11C29/12005
摘要： An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption.
摘要翻译：公开了内部电压产生电路和包括内部电压产生电路的半导体存储器件。内部电压产生电路包括第一电压产生电路，第二电压产生电路和第三电压产生电路。第一电压产生电路稳定第一外部电源电压以产生第一内部电压。第二电压产生电路稳定第一外部电源电压和第二外部电源电压，以产生具有高于第一内部电压的电压电平的第二内部电压。第三电压产生电路稳定第二内部电压以产生具有低于第二内部电压的电压电平的第三内部电压。因此，半导体存储器件可能对外部电源电压的变化不敏感，并且具有小的功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式