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1. 发明申请

US20060097773A1 Negative voltage generator circuit 失效
标题翻译：负电压发生器电路
公开(公告)号：US20060097773A1
公开(公告)日：2006-05-11
申请号：US11193814
申请日：2005-07-27
申请人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
发明人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.
摘要翻译：本发明涉及一种用于将半导体集成电路（IC）可靠地提供负电压的负电压产生电路。电荷泵送装置通过将电荷泵送到提供给第一节点和第二节点之一的预定水平来产生负电压。控制装置响应于负电压的电平，以预定间隔交替地提供按时钟交替的第一和第二泵送时钟信号。泵送控制器响应于第一和第二泵送时钟信号控制提供给第一节点和第二节点的电荷量。此外，复位控制器将电荷泵送装置的第一节点和第二节点复位为当第一和第二抽运时钟信号失活时的负电压的电平。

2. 发明授权

US07282986B2 Negative voltage generator circuit 失效
标题翻译：负电压发生器电路
公开(公告)号：US07282986B2
公开(公告)日：2007-10-16
申请号：US11193814
申请日：2005-07-27
申请人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
发明人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.
摘要翻译：本发明涉及一种用于将半导体集成电路（IC）可靠地提供负电压的负电压产生电路。电荷泵送装置通过将电荷泵送到提供给第一节点和第二节点之一的预定水平来产生负电压。控制装置响应于负电压的电平，以预定间隔交替地提供按时钟交替的第一和第二泵送时钟信号。泵送控制器响应于第一和第二泵送时钟信号控制提供给第一节点和第二节点的电荷量。此外，复位控制器将电荷泵送装置的第一节点和第二节点复位为当第一和第二抽运时钟信号失活时的负电压的电平。

3. 发明授权

US07149131B2 Semiconductor memory device and internal voltage generating method thereof 有权
标题翻译：半导体存储器件及其内部电压产生方法
公开(公告)号：US07149131B2
公开(公告)日：2006-12-12
申请号：US11024969
申请日：2004-12-30
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/4076
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.
摘要翻译：半导体存储器件通过保持内部电源电压和核心电压的质量来降低功耗。半导体存储器件在预充电期间充分保持核心电压来降低功耗。该半导体存储装置包括接收外部控制信号以输出有效信号和预充电信号的指令解码器，接收有效信号的内部电源电压产生控制单元和用于激活内部电力电压有源信号预定时间的预充电信号，接收有效信号的核心电压产生控制单元，用于激活核心电压有源信号预定时间的预充电信号和内部电源电压有效信号;内部电源电压产生单元，用于在激活期间内产生内部电源电压内部电源电压有效信号; 以及核心电压产生单元，用于在核心电压有源信号的激活期间产生核心电压。

4. 发明申请

US20060092743A1 Semiconductor memory device and internal voltage generating method thereof 有权
公开(公告)号：US20060092743A1
公开(公告)日：2006-05-04
申请号：US11024969
申请日：2004-12-30
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.

5. 发明申请

US20060050589A1 Power voltage supplier of semiconductor memory device 有权
标题翻译：半导体存储器件的电源供应商
公开(公告)号：US20060050589A1
公开(公告)日：2006-03-09
申请号：US11020244
申请日：2004-12-27
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147
摘要： The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.
摘要翻译：本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

6. 发明申请

US20080175088A1 Power voltage supplier of semiconductor memory device 有权
标题翻译：半导体存储器件的电源供应商
公开(公告)号：US20080175088A1
公开(公告)日：2008-07-24
申请号：US12068273
申请日：2008-02-05
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147
摘要： The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.
摘要翻译：本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

7. 发明授权

US07349282B2 Power voltage supplier of semiconductor memory device 有权
公开(公告)号：US07349282B2
公开(公告)日：2008-03-25
申请号：US11020244
申请日：2004-12-27
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147
摘要： The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

8. 发明授权

US07668034B2 Power voltage supplier of semiconductor memory device 有权
标题翻译：半导体存储器件的电源供应商
公开(公告)号：US07668034B2
公开(公告)日：2010-02-23
申请号：US12068273
申请日：2008-02-05
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147
摘要： The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.
摘要翻译：本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

9. 发明授权

US08314476B2 Semiconductor chip and semiconductor wafer 有权
标题翻译：半导体芯片和半导体晶圆
公开(公告)号：US08314476B2
公开(公告)日：2012-11-20
申请号：US12833672
申请日：2010-07-09
申请人： Jun-Gi Choi , Jong-Chern Lee
发明人： Jun-Gi Choi , Jong-Chern Lee
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.
摘要翻译：半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

10. 发明申请

US20110001552A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110001552A1
公开(公告)日：2011-01-06
申请号：US12615876
申请日：2009-11-10
申请人： Sang-Hoon SHIN , Hyung-Dong Lee , Jun-Gi Choi
发明人： Sang-Hoon SHIN , Hyung-Dong Lee , Jun-Gi Choi
IPC分类号： H01H37/76
CPC分类号： H01L23/5256 , G11C17/16 , G11C17/18 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
摘要翻译：半导体器件包括：第一传输线和布置在不同层的第二传输线; 与第一传输线和第二传输线耦合的接触熔丝; 功率驱动器，被配置为向所述接触保险丝施加电应力; 以及熔丝状态输出单元，被配置为输出具有与所述接触熔丝的电连接状态对应的逻辑电平的熔丝状态信号。

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