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1. 发明授权

US06169507A Stabilization of single loop sigma-delta modulators of a high order 有权
标题翻译：高阶单环Σ-Δ调制器的稳定化
公开(公告)号：US06169507A
公开(公告)日：2001-01-02
申请号：US09277874
申请日：1999-03-29
申请人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Marco Angelici , Fabio Osnato
发明人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Marco Angelici , Fabio Osnato
IPC分类号： H03M302
CPC分类号： H03M3/434
摘要： A sigma-delta modulator of second or higher order includes two or more integrating stages, and a comparator connected in cascade to the integration stages. A signal having a logic level +1 is generated when an input signal to the sigma-delta modulator is positive, and a signal having a logic value −1 is generated when the input signal is negative. Regardless of its absolute value, a feedback line includes a low-pass filter and an adder circuit for adding a feedback signal. The signal output by the last of the integrating stages is filtered by the low-pass filter. The sigma-delta modulator further includes a second comparator having an input connected in common to the input of the first comparator and an output connected to an input of the low-pass filter. The second comparator outputs a logic signal having a positive value when the input signal is positive, and outputs a logic signal having a negative value when the input signal is negative. The second comparator also outputs a signal having an increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value.
摘要翻译：第二或更高阶的Σ-Δ调制器包括两个或更多个积分级，以及一个级联连接到积分级的比较器。当向Σ-Δ调制器的输入信号为正时，产生具有逻辑电平+1的信号，并且当输入信号为负时产生具有逻辑值-1的信号。无论其绝对值如何，反馈线包括用于添加反馈信号的低通滤波器和加法器电路。最后一个积分级输出的信号由低通滤波器滤波。 Σ-Δ调制器还包括第二比较器，其具有与第一比较器的输入共同连接的输入端和连接到低通滤波器的输入端的输出端。当输入信号为正时，第二比较器输出具有正值的逻辑信号，并且当输入信号为负时输出具有负值的逻辑信号。当输入信号超过增加值的一个或多个预定阈值时，第二比较器还输出具有增加的逻辑电平的信号。

2. 发明授权

US5818376A Introduction of a whitener signal in a Sigma Delta modulator in the conversion of digital audio signals 失效
标题翻译：在Sigma Delta调制器中引入一个增白信号转换数字音频信号
公开(公告)号：US5818376A
公开(公告)日：1998-10-06
申请号：US798737
申请日：1997-02-13
申请人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina
发明人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina
IPC分类号： H03M7/32 , H03M1/08 , H03M1/66 , H03M7/00
CPC分类号： H03M7/3008 , H03M7/3028 , H03M7/3042
摘要： A method of injecting a whitening random signal in a Sigma Delta modulator with a high-pass transfer function of a quantization noise filter of a certain order, for converting a digital audio signal sampled at a certain clock frequency into an analog signal, comprises the steps of generating a flat-spectrum dither signal, filtering the dither signal with a high-pass transfer function of an order higher than the order of the transfer function of the Sigma Delta modulator, and summing the filtered signal to the sampled digital audio signal, quantized by the modulator. The method prevents the occurrence of disturbances that would otherwise occur as a result of intermodulation of subtle colorations observable in the vicinity of the Nyquist frequency. The disclosed hardware implementation of the method adds little to the hardware complexity.
摘要翻译：一种在具有一定次序的量化噪声滤波器的高通传递函数的Sigma Delta调制器中注入白化随机信号的方法，用于将以某一时钟频率采样的数字音频信号转换为模拟信号，包括步骤产生平坦频抖动信号，以高于Sigma Delta调制器的传递函数的阶数的高通传递函数对抖动信号进行滤波，并将经滤波的信号与采样的数字音频信号相加，量化通过调制器。该方法防止了由于在奈奎斯特频率附近可观察到的微妙着色而导致的干扰的发生。所公开的该方法的硬件实现对硬件复杂性几乎没有增加。

3. 发明授权

US5929621A Generation of temperature compensated low noise symmetrical reference voltages 有权
标题翻译：生成温度补偿低噪声对称参考电压
公开(公告)号：US5929621A
公开(公告)日：1999-07-27
申请号：US175161
申请日：1998-10-19
申请人： Marco Angelici , Sandro Dalle Feste , Nadia Serina , Marco Bianchessi
发明人： Marco Angelici , Sandro Dalle Feste , Nadia Serina , Marco Bianchessi
IPC分类号： H01L27/04 , G05F1/10 , G05F1/56 , G05F3/26 , H01L21/822 , G05F3/16
CPC分类号： G05F3/262 , G05F1/561 , Y10S323/907
摘要： Generation of symmetrical temperature compensated reference voltages in mixed type integrated circuits (digital and analog) having a superior PSRR is provided. Such a circuit includes a voltage-to-current conversion stage of a temperature independent bandgap voltage for producing a differential pair of currents that are applied as inputs to a pair of resistor feedback operational amplifiers. The feedback resistors are integrated in an interlaced form with a resistor employed in the conversion stage so that they have the same thermal gradient. Output of the operational amplifiers provides two temperature compensated low noise symmetrical reference voltages.
摘要翻译：提供具有优异PSRR的混合型集成电路（数字和模拟）中对称温度补偿参考电压的生成。这种电路包括与温度无关的带隙电压的电压 - 电流转换级，用于产生用作输入到一对电阻反馈运算放大器的差分电流对。反馈电阻器以交错形式集成在转换级中使用的电阻器，使得它们具有相同的热梯度。运算放大器的输出提供两个温度补偿低噪声对称参考电压。

4. 发明授权

US5886656A Digital microphone device 失效
标题翻译：数字麦克风设备
公开(公告)号：US5886656A
公开(公告)日：1999-03-23
申请号：US653427
申请日：1996-05-24
申请人： Sandro Dalle Feste , Marco Bianchessi , Nadia Serina
发明人： Sandro Dalle Feste , Marco Bianchessi , Nadia Serina
IPC分类号： H04R1/00 , H04R3/00 , H03M3/02
CPC分类号： H04R3/00 , H04R1/005
摘要： A microphone device having input terminals for receiving an input analog signal and output terminals to produce an output digital signal. The microphone device includes a converter circuit having input terminals coupled to the input terminals of the microphone device and an output terminal coupled to the output terminals of the microphone and an output terminal coupled to the output terminals of the microphone device. The device includes an analog input interface having input terminals corresponding to the input terminals of the microphone device and first and second output terminals to produce an amplified analog voltage signal, a converter circuit having first and second input terminals corresponding respectively to the first and the second output terminals of the analog input interface and an output terminal to produce a digital voltage signal and a parallel to serial digital output interface having an input terminal corresponding to the output terminal of the converter circuit and output terminals corresponding to the output terminals of the microphone device. The converter circuit desirably includes a signal modulator circuit having an input terminal coupled to the input terminals of the converter circuit and an output terminal to produce an intermediate digital voltage signal and a signal sampler circuit having an input terminal corresponding to the output terminal of the signal modulator circuit and an output terminal corresponding to the output terminal of the converter circuit.
摘要翻译：麦克风装置具有用于接收输入模拟信号的输入端和输出端以产生输出数字信号。麦克风装置包括转换器电路，其具有耦合到麦克风装置的输入端的输入端和耦合到麦克风的输出端的输出端和耦合到麦克风装置的输出端的输出端。该装置包括模拟输入接口，其具有与麦克风装置的输入端相对应的输入端和第一和第二输出端以产生放大的模拟电压信号;转换器电路，具有分别对应于第一和第二输入端的第一和第二输入端模拟输入接口的输出端和输出端产生数字电压信号和并行到串行数字输出接口，其具有对应于转换器电路的输出端的输入端和与麦克风装置的输出端对应的输出端。转换器电路理想地包括信号调制器电路，其具有耦合到转换器电路的输入端的输入端和产生中间数字电压信号的输出端和具有对应于信号的输出端的输入端的信号采样电路调制器电路和对应于转换器电路的输出端的输出端子。

5. 发明授权

US06487263B1 Decoding of a biphase modulated bitstream and relative self-synchronizing frequency divider with noninteger ratio 有权
标题翻译：双相调制比特流的解码和非整数比的相对自同步分频器
公开(公告)号：US06487263B1
公开(公告)日：2002-11-26
申请号：US09203704
申请日：1998-12-02
申请人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Marco Angelici
发明人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Marco Angelici
IPC分类号： H04L702
CPC分类号： H04L7/0066 , H04L7/0331 , H04L7/041 , H04L25/4904
摘要： A digital circuit generates a phase synchronization signal for a digital input signal coded according to a biphase modulation. The phase synchronization signal is derived from a clock signal having a higher frequency than the maximum switching frequency of the digital input signal. The frequency of the clock signal is divided with a fully digital divider circuit having a non-integer ratio. The divider is self-synchronizing with the input digital signal. Control signals are used to enable or disable switching of the frequency divider. These control signals are generated by two circuits which sample the input signal with the master clock signal and analyze triplets of consecutive sampling values.
摘要翻译：数字电路产生用于根据双相调制编码的数字输入信号的相位同步信号。相位同步信号是从具有比数字输入信号的最大开关频率高的频率的时钟信号导出的。时钟信号的频率与具有非整数比的全数字分频电路分开。分频器与输入数字信号自身同步。控制信号用于启用或禁用分频器的切换。这些控制信号由两个电路产生，两个电路用主时钟信号对输入信号进行采样，并分析三个连续的采样值。

6. 发明授权

US6094488A Dynamic computation of the ratio between two bitstreams representing slowly varying quantities and Dolby Pro Logic decoder 失效
标题翻译：动态计算代表缓慢变化量的两个比特流之间的比率和杜比定向逻辑解码器
公开(公告)号：US6094488A
公开(公告)日：2000-07-25
申请号：US970845
申请日：1997-11-14
申请人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Davide Sanguinetti
发明人： Marco Bianchessi , Sandro Dalle Feste , Nadia Serina , Davide Sanguinetti
IPC分类号： H04S1/00 , H04R5/00
CPC分类号： H04S1/007
摘要： The ratio y(n) of two digital values, respectively a(n) and b(n), representing the n.sup.th elements of two respective sequences of digital input data representing two quantities slowly varying in time, is obtained by computingy(n)=y(n-1)+g*[a(n)-b(n)*y(n-1)]wherein g represents a multiplying factor. Within the domain of the z transform, the expression becomes:Y(z)=z.sup.-1 *Y(z)+g[A(z)-B(z)conv Y(z)*z.sup.-1where conv indicates an operation of convolution and which, for input sequences corresponding to signals filtered through a lowpass filter with a time constant greater than or equal to 3 msec is simplified to: ##EQU1## The approximation is exceptionally good and computation thereof may be achieved by the use of relatively simple hardware, without severely burdening the workload of a microprocessor.
摘要翻译：通过计算y（n）来获得表示代表缓慢变化的两个数量的数字输入数据的两个相应序列的第n个元素的分别为a（n）和b（n）的两个数字值的比率y（n） = y（n-1）+ g * [a（n）-b（n）* y（n-1）]其中，g表示倍增系数。在z变换的域内，表达式变为：Y（z）= z-1 * Y（z）+ g [A（z）-B（z）conv Y（z）* z-1其中，conv表示对于卷积的操作，对于对应于通过时间常数大于或等于3毫秒的低通滤波器滤波的信号的输入序列，简化为：近似值非常好，并且可以通过使用相对简单的硬件来实现其计算，而不会严重负担微处理器的工作量。

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