专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160056210A1 WORD LINE CONNECTION FOR MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
标题翻译：用于存储器件的字线连接及其制造方法
公开(公告)号：US20160056210A1
公开(公告)日：2016-02-25
申请号：US14463113
申请日：2014-08-19
申请人： SANDISK 3D LLC
发明人： Seje TAKAKI
IPC分类号： H01L27/24 , H01L21/768 , H01L21/3213 , H01L27/115
CPC分类号： H01L27/2481 , H01L21/32139 , H01L21/76892 , H01L27/0688 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L45/1226 , H01L45/141 , H01L45/145 , H01L45/149 , H01L45/16
摘要： A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.
摘要翻译：三维单片存储器件包括至少一个器件区域和多个接触区域，每个接触区域包括交替的多个导电字线接触层和位于衬底上的绝缘层的堆叠，其中多个接触区域中的堆叠通过绝缘材料彼此分离，并且桥连接器包括在第一接触区域中的第一堆叠体的第一导电字线接触层和第二层叠体的第二导电字线接触层之间延伸的导电材料第二接触区域，其中第一字线接触层在基本上平行于衬底的主表面的第一接触电平中延伸，而第二字线接触层在基本上平行于衬底的主表面的第二接触电平中延伸，不同于第一级。

2. 发明申请

US20170077184A1 THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS 审中-公开
标题翻译：包含自对准存储元件的三维电阻随机存取存储器
公开(公告)号：US20170077184A1
公开(公告)日：2017-03-16
申请号：US14851296
申请日：2015-09-11
申请人： SanDisk 3D LLC
发明人： Shin KIKUCHI , Kazushi KOMEDA , Takuya FUTASE , Teruyuki MINE , Seje TAKAKI , Eiji HAYASHI , Toshihide TOBITSUKA
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1633
摘要： An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
摘要翻译：绝缘体线和第一导电材料层的交替材料堆叠形成在衬底上，并被图案化以提供绝缘层和第一导电线的交替堆叠。可以在第一导电材料层的物理暴露的侧壁上选择性地沉积金属以形成金属线，而不会从绝缘体线的表面生长。金属线被氧化以形成与第一导电线的侧壁自对准的金属氧化物线。垂直延伸的第二导电线可以形成为在绝缘体线的交替堆叠和第一导电线之间的大致柱状结构的二维阵列。金属氧化物线在第一和第二导电线的交点处的每个部分构成用于电阻随机存取存储器（ReRAM）器件的电阻性存储元件。

3. 发明申请

US20160260775A1 PARALLEL BIT LINE THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：并行线三维电阻随机存取存储器
公开(公告)号：US20160260775A1
公开(公告)日：2016-09-08
申请号：US14635419
申请日：2015-03-02
申请人： SANDISK 3D LLC
发明人： Seje TAKAKI
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0069 , G11C13/0097 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.
摘要翻译：电阻随机存取存储器（ReRAM）阵列包括位于衬底上的线堆栈结构。线堆叠结构沿着第一水平方向横向间隔开，并且沿着与第一水平方向不同的第二水平方向延伸。每个线堆叠结构包括交替的多个字线和位线。包括存储材料线结构，本征半导体材料线结构和掺杂半导体材料线结构的插入线堆叠位于交替的多个字线和位线之间的字线和位线的每个垂直相邻对之间。垂直选择器线的二维阵列用作激活字线和位线之间的半导体通道的栅电极。可以在ReRAM阵列内编程和/或测量与激活的半导体通道接触的记忆材料线结构的电阻。

4. 发明申请

US20150179577A1 MULTILEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING THEREOF 有权
标题翻译：多重联系3D内存阵列及其制作方法
公开(公告)号：US20150179577A1
公开(公告)日：2015-06-25
申请号：US14643211
申请日：2015-03-10
申请人： SANDISK 3D LLC
发明人： Toshihide TOBITSUKA , Seje TAKAKI
IPC分类号： H01L23/535 , H01L27/24 , H01L21/768 , H01L27/115
CPC分类号： H01L23/535 , H01L21/76895 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L27/249 , H01L2924/0002 , H01L2924/00
摘要： A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.
摘要翻译：多级设备包括至少一个设备区域和至少一个接触区域。接触区域具有交替的多个导电层和位于衬底上方的多个电绝缘层的堆叠。多个导电层在接触区域中形成阶梯图案，其中每个相应的电绝缘层包括侧壁，并且堆叠中的相应的下面的导电层横向延伸超过侧壁。可选地，可以形成多个导电通孔连接件，其具有在相同水平平面内的顶表面，其底表面接触位于不同水平的相应导电层，并且通过至少一个沟槽隔离结构彼此隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式