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1. 发明申请

US20150279439A1 NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME 有权
标题翻译：非易失性存储器件和具有该存储器件的存储器件
公开(公告)号：US20150279439A1
公开(公告)日：2015-10-01
申请号：US14593171
申请日：2015-01-09
申请人： Suk-soo PYO , Hyuntaek JUNG
发明人： Suk-soo PYO , Hyuntaek JUNG
IPC分类号： G11C11/16 , G11C5/06
CPC分类号： G11C11/1673 , G11C5/025 , G11C5/06 , G11C7/062 , G11C8/14 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing complementary data, thereby increasing or maximizing sensing margin. Also, the nonvolatile memory device connects a plurality of true cell/complementary cells to a word line, thereby markedly reducing the size of a memory cell array.
摘要翻译：根据本发明构思的非易失性存储器件从存储数据的真实单元和存储互补数据的互补单元执行读取操作，从而增加或最大化感测余量。此外，非易失性存储器件将多个真实单元/互补单元连接到字线，从而显着地减小了存储单元阵列的尺寸。

2. 发明授权

US08208327B2 Semiconductor memory device and data read method thereof 有权
标题翻译：半导体存储器件及其数据读取方法
公开(公告)号：US08208327B2
公开(公告)日：2012-06-26
申请号：US12794033
申请日：2010-06-04
申请人： Suk-Soo Pyo
发明人： Suk-Soo Pyo
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the isolation unit configured to electrically connect or isolate the first bitline pair to or from the second bitline pair, and a sense amplifier electrically connected to the second bitline pair, the sense amplifier configured to sense a voltage difference of the second bitline pair, wherein the isolation circuit isolates one of the connections between the first bitline pair and the second bitline pair while the sense amplifier senses the voltage difference of the second bitline pair.
摘要翻译：半导体存储器件包括由第一均衡器电路等于第一电压电平的第一位线对，由第二均衡器电路等于第二电压电平的第二位线对，设置在第一位线对和第二位线之间的隔离电路所述隔离单元被配置为将所述第一位线对电连接到所述第二位线对或从所述第二位线对隔离，以及电连接到所述第二位线对的读出放大器，所述读出放大器被配置为感测所述第二位线对的电压差，其中所述隔离电路隔离所述第一位线对和所述第二位线对之间的连接中的一个，同时所述读出放大器感测所述第二位线对的电压差。

3. 发明申请

US20080175079A1 Test scheme for fuse circuit 审中-公开
标题翻译：保险丝电路测试方案
公开(公告)号：US20080175079A1
公开(公告)日：2008-07-24
申请号：US12008468
申请日：2008-01-11
申请人： Soon-Keun Jeon , Se-Hyun Hwang , Suk-Soo Pyo
发明人： Soon-Keun Jeon , Se-Hyun Hwang , Suk-Soo Pyo
IPC分类号： G11C29/00 , G11C7/00 , G11C17/18
CPC分类号： G11C29/02 , G11C29/027 , G11C29/846
摘要： Provided is an apparatus and a method for testing an electrical fuse. In accordance therewith: a first test is performed on a plurality of memory cells arranged with a plurality of rows and a plurality of columns; a line related to a defective cell is repaired with a redundant line by using an electrical fuse; data outputted from the redundant line is set with a predetermined value; performing a second test on the plurality of memory cells; and a determination is made of whether or not data outputted from the line related to a defective cell has the predetermined value.
摘要翻译：提供了一种用于测试电熔丝的装置和方法。与此相对应：对多行和多列排列的多个存储单元执行第一测试; 通过使用电熔丝用冗余线修复与缺陷电池相关的线; 从冗余线输出的数据被设定为预定值; 对所述多个存储器单元执行第二测试; 并且确定从与缺陷单元相关的行输出的数据是否具有预定值。

4. 发明申请

US20060087904A1 Memory device capable of refreshing data using buffer and refresh method thereof 有权
标题翻译：能够使用缓冲器刷新数据的存储装置及其刷新方法
公开(公告)号：US20060087904A1
公开(公告)日：2006-04-27
申请号：US11256879
申请日：2005-10-24
申请人： Suk-soo Pyo , Hyun-taek Jung , Min-Yeol Ha
发明人： Suk-soo Pyo , Hyun-taek Jung , Min-Yeol Ha
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40603 , G11C11/40607 , G11C11/40618
摘要： An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.
摘要翻译：集成电路存储器件包括存储器系统内的多个存储器和刷新控制器。刷新控制器被配置为产生刷新请求信号。多个存储器响应于刷新请求信号包括多个存储器组。附加存储器包括：缓冲器单元，被配置为产生刷新指示信号到多个存储器组中的第一组，并且响应于接收刷新指令而接收寻址到多个存储器组中的第一组的缓冲器写入数据。从多个存储器组中的一个存储器访问中断信号。多个存储体组和缓冲单元可以是分离的DRAM芯片。

5. 发明授权

US09691459B2 Semiconductor memory device including shorted variable resistor element of memory cell 有权
公开(公告)号：US09691459B2
公开(公告)日：2017-06-27
申请号：US15249845
申请日：2016-08-29
申请人： Bo-young Seo , Suk-soo Pyo , Gwan-hyeob Koh , Yong-kyu Lee , Dae-shik Kim
发明人： Bo-young Seo , Suk-soo Pyo , Gwan-hyeob Koh , Yong-kyu Lee , Dae-shik Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C7/14 , G11C11/1673 , G11C13/004 , G11C29/028 , G11C29/50008 , G11C2013/0054 , G11C2029/4402
摘要： A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

6. 发明申请

US20110122716A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF 审中-公开
标题翻译：动态随机访问存储器件及其确定周期的方法
公开(公告)号：US20110122716A1
公开(公告)日：2011-05-26
申请号：US13015833
申请日：2011-01-28
申请人： Suk-Soo PYO , Uk-Song KANG
发明人： Suk-Soo PYO , Uk-Song KANG
IPC分类号： G11C29/42
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

7. 发明授权

US07755966B2 Memory device performing a partial refresh operation based on accessed and/or refreshed memory blocks and method thereof 有权
标题翻译：基于访问和/或刷新的存储器块执行部分刷新操作的存储器件及其方法
公开(公告)号：US07755966B2
公开(公告)日：2010-07-13
申请号：US11975021
申请日：2007-10-17
申请人： Suk-Soo Pyo , Hyun-Taek Jung
发明人： Suk-Soo Pyo , Hyun-Taek Jung
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40622
摘要： The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit circuit for storing refresh check bits corresponding to the memory blocks, respectively; a block select control circuit for setting refresh check bits of memory blocks to be refreshed to a checked state according to a first control of the memory controller; a using check bit circuit for storing using check bits corresponding to the memory blocks, respectively; a using check control circuit for setting refresh check bits of memory blocks to which access is requested to a checked state according to a second control of the memory controller; and a partial refresh control circuit for controlling the refresh operation such that memory blocks corresponding to checked using check bits or checked refresh check bits are refreshed according to a third control of the memory controller.
摘要翻译：本发明提供了一种存储器件，其包括具有多个存储器块的存储单元阵列; 用于控制相对于存储块的刷新操作的存储器控制器; 刷新检查位电路，用于分别存储对应于存储块的刷新校验位; 块选择控制电路，用于根据存储器控制器的第一控制将要刷新的存储块的刷新校验位设置为检查状态; 使用校验位电路，分别使用与存储块对应的校验位来存储; 使用检查控制电路，用于根据存储器控制器的第二控制将请求访问的存储块的刷新校验位设置为检查状态; 以及部分刷新控制电路，用于控制刷新操作，使得根据存储器控制器的第三控制刷新与使用校验位或检查刷新校验位检查的对应的存储器块。

8. 发明申请

US20160343421A1 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：包括其的存储器件和存储器系统
公开(公告)号：US20160343421A1
公开(公告)日：2016-11-24
申请号：US15068580
申请日：2016-03-12
申请人： Suk-Soo PYO
发明人： Suk-Soo PYO
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C5/04 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C29/023 , G11C29/028
摘要： A memory device may include a data region, a reference region, a resistor circuit, and a sense amplifier. The data region may include a plurality of data memory cells coupled between a first bit line and a first source line. The data region may provide a data voltage corresponding to data stored in each of the data memory cells. The reference region may include a plurality of reference memory cells coupled between a reference bit line and a reference source line. The reference region may provide a reference voltage. The resistor circuit may include one or more resistors, and is coupled between the reference source line and a power source line. The sense amplifier may provide an output voltage by comparing the data voltage and the reference voltage. The power source line may be either a ground voltage or a negative voltage.
摘要翻译：存储器件可以包括数据区，参考区，电阻电路和读出放大器。数据区域可以包括耦合在第一位线和第一源极线之间的多个数据存储单元。数据区域可以提供对应于存储在每个数据存储单元中的数据的数据电压。参考区域可以包括耦合在参考位线和参考源极线之间的多个参考存储单元。参考区域可以提供参考电压。电阻器电路可以包括一个或多个电阻器，并且耦合在参考源极线和电源线之间。读出放大器可以通过比较数据电压和参考电压来提供输出电压。电源线可以是接地电压或负电压。

9. 发明授权

US07263020B2 Memory device capable of refreshing data using buffer and refresh method thereof 有权
标题翻译：能够使用缓冲器刷新数据的存储装置及其刷新方法
公开(公告)号：US07263020B2
公开(公告)日：2007-08-28
申请号：US11256879
申请日：2005-10-24
申请人： Suk-soo Pyo , Hyun-taek Jung , Min-yeol Ha
发明人： Suk-soo Pyo , Hyun-taek Jung , Min-yeol Ha
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40603 , G11C11/40607 , G11C11/40618
摘要： An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.
摘要翻译：集成电路存储器件包括存储器系统内的多个存储器和刷新控制器。刷新控制器被配置为产生刷新请求信号。多个存储器响应于刷新请求信号包括多个存储器组。附加存储器包括：缓冲器单元，被配置为产生刷新指示信号到多个存储器组中的第一组，并且响应于接收刷新指令而接收寻址到多个存储器组中的第一组的缓冲器写入数据。从多个存储器组中的一个存储器访问中断信号。多个存储体组和缓冲单元可以是分离的DRAM芯片。

10. 发明授权

US07187608B2 System and method for controlling the access and refresh of a memory 有权
标题翻译：用于控制存储器的访问和刷新的系统和方法
公开(公告)号：US07187608B2
公开(公告)日：2007-03-06
申请号：US11193805
申请日：2005-07-28
申请人： Min-Yeol Ha , Suk-Soo Pyo , Hyun-Taek Jung
发明人： Min-Yeol Ha , Suk-Soo Pyo , Hyun-Taek Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G06F12/0875 , G11C11/406 , G11C11/40603
摘要： The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.
摘要翻译：本发明提供了一种存储器和存储器控制系统，其中除主要存储器之外的一个情况除外，主存储器优先于刷新操作的读或写操作。另一方面，高速缓冲存储器优先于对读或写操作的刷新操作。特殊情况是当启用缓存刷新并且高速缓存中的数据有效时接收到存储器读取信号。在这种特殊情况下，缓存内存的刷新被延迟。在某些读取操作期间，特定存储器块中的数据也被写入高速缓存，并且不执行从缓存的回写。这减少了回写操作的数量，并且消除了由刷新操作引起的延迟。

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