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1. 发明申请

US20110080795A1 SEMICONDUCTOR MEMORY DEVICE AND DATA READ METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据读取方法
公开(公告)号：US20110080795A1
公开(公告)日：2011-04-07
申请号：US12794033
申请日：2010-06-04
申请人： Suk-Soo PYO
发明人： Suk-Soo PYO
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the isolation unit configured to electrically connect or isolate the first bitline pair to or from the second bitline pair, and a sense amplifier electrically connected to the second bitline pair, the sense amplifier configured to sense a voltage difference of the second bitline pair, wherein the isolation circuit isolates one of the connections between the first bitline pair and the second bitline pair while the sense amplifier senses the voltage difference of the second bitline pair.
摘要翻译：半导体存储器件包括由第一均衡器电路等于第一电压电平的第一位线对，由第二均衡器电路等于第二电压电平的第二位线对，设置在第一位线对和第二位线之间的隔离电路所述隔离单元被配置为将所述第一位线对电连接到所述第二位线对或从所述第二位线对隔离，以及电连接到所述第二位线对的读出放大器，所述读出放大器被配置为感测所述第二位线对的电压差，其中所述隔离电路隔离所述第一位线对和所述第二位线对之间的连接中的一个，同时所述读出放大器感测所述第二位线对的电压差。

2. 发明申请

US20110122716A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF 审中-公开
标题翻译：动态随机访问存储器件及其确定周期的方法
公开(公告)号：US20110122716A1
公开(公告)日：2011-05-26
申请号：US13015833
申请日：2011-01-28
申请人： Suk-Soo PYO , Uk-Song KANG
发明人： Suk-Soo PYO , Uk-Song KANG
IPC分类号： G11C29/42
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

3. 发明申请

US20160343421A1 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：包括其的存储器件和存储器系统
公开(公告)号：US20160343421A1
公开(公告)日：2016-11-24
申请号：US15068580
申请日：2016-03-12
申请人： Suk-Soo PYO
发明人： Suk-Soo PYO
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C5/04 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C29/023 , G11C29/028
摘要： A memory device may include a data region, a reference region, a resistor circuit, and a sense amplifier. The data region may include a plurality of data memory cells coupled between a first bit line and a first source line. The data region may provide a data voltage corresponding to data stored in each of the data memory cells. The reference region may include a plurality of reference memory cells coupled between a reference bit line and a reference source line. The reference region may provide a reference voltage. The resistor circuit may include one or more resistors, and is coupled between the reference source line and a power source line. The sense amplifier may provide an output voltage by comparing the data voltage and the reference voltage. The power source line may be either a ground voltage or a negative voltage.
摘要翻译：存储器件可以包括数据区，参考区，电阻电路和读出放大器。数据区域可以包括耦合在第一位线和第一源极线之间的多个数据存储单元。数据区域可以提供对应于存储在每个数据存储单元中的数据的数据电压。参考区域可以包括耦合在参考位线和参考源极线之间的多个参考存储单元。参考区域可以提供参考电压。电阻器电路可以包括一个或多个电阻器，并且耦合在参考源极线和电源线之间。读出放大器可以通过比较数据电压和参考电压来提供输出电压。电源线可以是接地电压或负电压。

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