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1. 发明授权

US09135139B2 Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions 有权
标题翻译：使用表达式在多线程程序中识别和再现并发违规的方法和系统
公开(公告)号：US09135139B2
公开(公告)日：2015-09-15
申请号：US13535334
申请日：2012-06-27
申请人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
发明人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F11/00 , G06F9/45 , G06F3/00 , G06F9/46 , G06F13/00 , G06F11/36
CPC分类号： G06F11/3688 , G06F8/70 , G06F11/36 , G06F11/3632
摘要： Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.
摘要翻译：公开了在多线程程序中识别和再现并发错误的方法和系统。本文公开的示例性方法包括定义数据类型。数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。这种关系在满足时会导致并发错误被检测到。符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

2. 发明授权

US08683243B2 Dynamic core selection for heterogeneous multi-core systems 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US08683243B2
公开(公告)日：2014-03-25
申请号：US13046031
申请日：2011-03-11
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

3. 发明申请

US20120233477A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US20120233477A1
公开(公告)日：2012-09-13
申请号：US13046031
申请日：2011-03-11
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F9/318 , G06F1/32
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

4. 发明申请

US20120079245A1 DYNAMIC OPTIMIZATION FOR CONDITIONAL COMMIT 审中-公开
标题翻译：动态优化条件咨询
公开(公告)号：US20120079245A1
公开(公告)日：2012-03-29
申请号：US12890638
申请日：2010-09-25
申请人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
发明人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3857
摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
摘要翻译：本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。虽然投机检查点能够在中止交易后快速有效地恢复。处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

5. 发明申请

US20110320766A1 APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE 审中-公开
标题翻译：用于提高功率的装置，方法和系统，通过与第二核心类型耦合的第一核心类型的性能效率
公开(公告)号：US20110320766A1
公开(公告)日：2011-12-29
申请号：US12826107
申请日：2010-06-29
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30076 , G06F9/30174 , G06F9/3879 , G06F9/4893 , Y02D10/24
摘要： An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.
摘要翻译：本文描述了一种用于将第一类型的处理器核与第二类型的共同设计的核耦合的装置和方法。对第一个核心上的程序代码执行进行监控，并且识别程序代码的热部分。这些热部分优化用于在共同设计的芯上执行，使得在随后遇到这些热部分时，优化的热部分在共同设计的核上执行。当共同设计的核心正在执行优化的热代码时，第一处理器核心可以处于低功率状态以节省功率或并行执行其他代码。此外，多个冷码线程可以在第一核心上流水线化，而多个热代码线程在共同设计的核心上进行流水线以实现最大性能。

6. 发明授权

US09501340B2 Mechanism for facilitating dynamic and efficient management of instruction atomicity violations in software programs at computing systems 有权
标题翻译：促进计算系统软件程序中指令原子性违规的动态和有效管理的机制
公开(公告)号：US09501340B2
公开(公告)日：2016-11-22
申请号：US13977690
申请日：2013-03-15
申请人： Nathan D. Dautenhahn , Justin E. Gottschlich , Gilles Pokam , Cristiano L. Pereira , Shiliang Hu , Klaus Danne , Rolf Kassa
发明人： Nathan D. Dautenhahn , Justin E. Gottschlich , Gilles Pokam , Cristiano L. Pereira , Shiliang Hu , Klaus Danne , Rolf Kassa
IPC分类号： G06F9/45 , G06F11/07 , G06F9/38 , G06F11/14
CPC分类号： G06F9/30145 , G06F9/3009 , G06F9/3895 , G06F9/3897 , G06F9/52 , G06F11/0724 , G06F11/1438 , G06F11/1484 , G06F11/3636
摘要： A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.
摘要翻译：描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。记录系统可以记录第一和第二宏指令之间的交织。该方法包括在发生时准确地重播第一和第二宏指令的交错记录。正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

7. 发明申请

US20160232077A1 TECHNIQUES FOR DETECTING RACE CONDITIONS 审中-公开
标题翻译：检测条件的技术
公开(公告)号：US20160232077A1
公开(公告)日：2016-08-11
申请号：US15026515
申请日：2013-12-12
申请人： Shiliang HU , Gilles A. POKAM , Cristiano L. PEREIRA , Justin E. GOTTSCHLICH
发明人： Shiliang HU , Gilles A. POKAM , Cristiano L. PEREIRA , Justin E. GOTTSCHLICH
IPC分类号： G06F11/36
CPC分类号： G06F11/3632 , G06F9/526 , G06F11/0715 , G06F11/0778 , G06F11/30 , G06F11/3409 , G06F11/3419 , G06F11/3466 , G06F11/366
摘要： Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及通过检测与这种访问相关联的所选择的高速缓存事件的发生来检测由应用程序的不同部分的未协调数据访问引起的竞争条件。一种装置包括处理器组件; 触发组件，用于由处理器组件执行以配置处理器组件的监控单元以检测与对一条数据的访问之间的竞争条件相关联的高速缓存事件，并且捕获处理器组件的状态的指示以生成监视响应于缓存事件的发生的数据; 以及用于由处理器组件执行以配置监视单元的计数器的计数器组件，以使得能够以小于高速缓存事件的每次出现的频率捕获处理器组件的状态的指示。描述和要求保护其他实施例。

8. 发明申请

US20150186178A1 Processor With Transactional Capability and Logging Circuitry To Report Transactional Operations 有权
标题翻译：具有事务功能和记录电路的处理器来报告事务操作
公开(公告)号：US20150186178A1
公开(公告)日：2015-07-02
申请号：US14142475
申请日：2013-12-27
申请人： Rolf Kassa , Justin E. Gottschlich , Shiliang Hu , Gilles A. Pokam , Robert C. Knauerhase
发明人： Rolf Kassa , Justin E. Gottschlich , Shiliang Hu , Gilles A. Pokam , Robert C. Knauerhase
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/528 , G06F11/0724 , G06F11/0772
摘要： A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.
摘要翻译：描述了一种处理器，其包括存储器访问冲突检测电路，以识别与正在由线程执行的事务有关的冲突，该线程相信它已经将信息锁定在存储器内。如果存储器访问冲突检测电路识别导致事务中止的冲突，则处理器还包括记录电路来构造和报告数据包。

9. 发明申请

US20140189256A1 PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE 有权
标题翻译：具有记录仪记录器的处理器，用于记录多个软件中的螺纹交叉
公开(公告)号：US20140189256A1
公开(公告)日：2014-07-03
申请号：US13729718
申请日：2012-12-28
申请人： TIM KRANICH , GILLES A. POKAM , JUSTIN E. GOTTSCHLICH , KLAUS DANNE , ROLF KASSA , SHILIANG HU , CRISTIANO L. PEREIRA
发明人： TIM KRANICH , GILLES A. POKAM , JUSTIN E. GOTTSCHLICH , KLAUS DANNE , ROLF KASSA , SHILIANG HU , CRISTIANO L. PEREIRA
IPC分类号： G06F12/08
CPC分类号： G06F9/526 , G06F11/3404 , G06F11/3409 , G06F11/3471 , G06F11/36 , G06F11/3636
摘要： A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.
摘要翻译：处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。块缓冲区是临时存储块，直到块被从处理器传出。

10. 发明申请

US20160116965A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开
公开(公告)号：US20160116965A1
公开(公告)日：2016-04-28
申请号：US14986678
申请日：2016-01-02
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

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