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1. 发明授权

US09478561B2 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09478561B2
公开(公告)日：2016-10-25
申请号：US14960776
申请日：2015-12-07
申请人： Chaeho Kim , Sangryol Yang , Woong Lee , SeungHyun Lim
发明人： Chaeho Kim , Sangryol Yang , Woong Lee , SeungHyun Lim
IPC分类号： H01L27/105 , H01L27/115 , H01L29/51 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/42348 , H01L29/513
摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.
摘要翻译：一种半导体存储器件包括：堆叠，其包括交替重复堆叠在衬底上的栅电极和绝缘层。细胞通道结构穿透堆叠。单元沟道结构包括与基板接触的第一半导体图案和第一半导体图案上的第一沟道图案。第一半导体图案延伸到从基板的表面到第一半导体图案的顶表面的第一高度。衬底上的虚拟通道结构，与堆叠间隔开。虚设通道结构包括接触衬底的第二半导体图案和第二半导体图案上的第二沟道图案。第二半导体图案延伸到从基板的表面到第二半导体图案的顶表面的第二高度。第一个高度大于第二个高度。

2. 发明申请

US20160240550A1 NON-VOLATILE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS 有权
标题翻译：非易失性存储器件，包括充电储存层
公开(公告)号：US20160240550A1
公开(公告)日：2016-08-18
申请号：US15043640
申请日：2016-02-15
申请人： JAEHUN JUNG , ZHILIANG XIA , DAEWOONG KANG , DAE SIN KIM , KWANG SOO SEOL , HOMIN SON , SEUNGHYUN LIM
发明人： JAEHUN JUNG , ZHILIANG XIA , DAEWOONG KANG , DAE SIN KIM , KWANG SOO SEOL , HOMIN SON , SEUNGHYUN LIM
IPC分类号： H01L27/115 , H01L29/792 , H01L29/423
CPC分类号： H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42364 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.
摘要翻译：非易失性存储器件包括堆叠在衬底上的栅极电极，穿过栅极并连接到衬底的半导体图案，以及半导体图案和栅电极之间的电荷存储层。电荷存储层包括半导体图形和栅电极之间的第一电荷存储层，第一电荷存储层和半导体图案之间的第二电荷存储层，以及第一电荷存储层和栅极之间的第三电荷存储层电极。第一电荷存储层的能带隙比第二和第三电荷存储层的能带隙小。第一电荷存储层比第二和第三电荷存储层厚。

3. 发明授权

US07804437B2 Analog-to-digital converter for accumulating reference voltages successively divided by two 有权
标题翻译：模数转换器，用于将参考电压累积到两个
公开(公告)号：US07804437B2
公开(公告)日：2010-09-28
申请号：US12292787
申请日：2008-11-26
申请人： Gunhee Han , Jeonghwan Lee , Seunghyun Lim
发明人： Gunhee Han , Jeonghwan Lee , Seunghyun Lim
IPC分类号： H03M1/34
CPC分类号： H03M1/46 , H03M1/123 , H03M1/667
摘要： An analog-to-digital converter includes a ½ powered signal generator configured to generate divided signals by successively dividing a full scale signal by 2 and output one of the divided signals, an accumulator configured to update a reference signal according to a current divided signal and a current output bit, and a comparator configured to compare the updated reference signal with an input signal and generate a next output bit.
摘要翻译：一种模拟数字转换器包括：1/2电源信号发生器，被配置为通过将满量程信号连续地除以2并输出一个分频信号来产生分频信号，累加器被配置为根据当前划分的信号更新参考信号;以及电流输出位和比较器，被配置为将更新的参考信号与输入信号进行比较，并产生下一个输出位。

4. 发明授权

US09490371B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09490371B2
公开(公告)日：2016-11-08
申请号：US14539043
申请日：2014-11-12
申请人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
发明人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
IPC分类号： H01L29/792 , H01L29/66 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
摘要翻译：非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

5. 发明申请

US20150194440A1 Nonvolatile Memory Devices And Methods Of Fabricating The Same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20150194440A1
公开(公告)日：2015-07-09
申请号：US14539043
申请日：2014-11-12
申请人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
发明人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/7926 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
摘要翻译：非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

6. 发明申请

US20130270625A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130270625A1
公开(公告)日：2013-10-17
申请号：US13838159
申请日：2013-03-15
申请人： Byong-hyun JANG , Janggn Yun , KwangSoo Seol , Jungdal Choi , Byongju Kim , Kwangmin Park , Junkyu Yang , SeungHyun Lim
发明人： Byong-hyun JANG , Janggn Yun , KwangSoo Seol , Jungdal Choi , Byongju Kim , Kwangmin Park , Junkyu Yang , SeungHyun Lim
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/1157 , H01L27/11582 , H01L29/7889
摘要： A three-dimensional (3D) semiconductor memory device includes a stack structure, a channel structure, and a vertical insulator. The stack structure includes gate patterns and insulating patterns which are alternately and repeatedly stacked on a substrate. A channel structure penetrates the stack structure and is connected to the substrate. A vertical insulator includes a high-k dielectric layer. The vertical insulator is covered by the channel structure and the high-k dielectric pattern of the vertical insulator is in contact with the gate patterns.
摘要翻译：三维（3D）半导体存储器件包括堆叠结构，沟道结构和垂直绝缘体。堆叠结构包括交替重复堆叠在基板上的栅极图案和绝缘图案。通道结构穿透堆叠结构并连接到基板。垂直绝缘体包括高k电介质层。垂直绝缘体被沟道结构覆盖，垂直绝缘体的高k电介质图案与栅极图案接触。

7. 发明申请

US20120267701A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120267701A1
公开(公告)日：2012-10-25
申请号：US13425584
申请日：2012-03-21
申请人： Soodoo Chae , Kihyun Hwang , Hanmei Choi , SeungHyun Lim
发明人： Soodoo Chae , Kihyun Hwang , Hanmei Choi , SeungHyun Lim
IPC分类号： H01L29/78
CPC分类号： H01L27/11582 , G11C5/02 , G11C16/0483 , H01L27/1157
摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.
摘要翻译：非易失性存储器件包括垂直堆叠的非易失性存储单元。非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。第二栅极图案也从第一栅极图案分离小于第一和第二厚度之和的距离。

8. 发明申请

US20160225785A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160225785A1
公开(公告)日：2016-08-04
申请号：US14960776
申请日：2015-12-07
申请人： Chaeho KIM , Sangryol Yang , Woong Lee , SeungHyun Lim
发明人： Chaeho KIM , Sangryol Yang , Woong Lee , SeungHyun Lim
IPC分类号： H01L27/115 , H01L29/423 , H01L29/51
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/42348 , H01L29/513
摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.
摘要翻译：一种半导体存储器件包括：堆叠，其包括交替重复堆叠在衬底上的栅电极和绝缘层。细胞通道结构穿透堆叠。单元沟道结构包括与基板接触的第一半导体图案和第一半导体图案上的第一沟道图案。第一半导体图案延伸到从基板的表面到第一半导体图案的顶表面的第一高度。衬底上的虚拟通道结构，与堆叠间隔开。虚设通道结构包括接触衬底的第二半导体图案和第二半导体图案上的第二沟道图案。第二半导体图案延伸到从基板的表面到第二半导体图案的顶表面的第二高度。第一个高度大于第二个高度。

9. 发明授权

US08723597B2 Switched capacitor circuit 有权
标题翻译：开关电容电路
公开(公告)号：US08723597B2
公开(公告)日：2014-05-13
申请号：US13395277
申请日：2010-07-12
申请人： Gunhee Han , Youngcheol Chae , Inhee Lee , Dongmyung Lee , Seunghyun Lim , Ji Min Cheon
发明人： Gunhee Han , Youngcheol Chae , Inhee Lee , Dongmyung Lee , Seunghyun Lim , Ji Min Cheon
IPC分类号： H03F1/02 , H03F1/14 , H03K17/00 , H03F3/00
CPC分类号： H03F3/005 , H03F3/211 , H03F3/45475 , H03F3/45928 , H03F2203/45512 , H03F2203/45514 , H03F2203/45534 , H03F2203/45631 , H03F2203/45644 , H03F2203/45724 , H03F2203/45726 , H03H19/004
摘要： According to the present invention, a switched capacitor circuit comprises: an inverting amplifier for removing the offset by using a chopper stabilization circuit; a sampling unit which is connected between an input terminal and the inverting amplifier; and a feedback unit which is connected to the inverting amplifier in parallel.
摘要翻译：根据本发明，开关电容电路包括：反相放大器，用于通过使用斩波稳定电路去除偏移; 连接在输入端和反相放大器之间的采样单元; 以及并联连接到反相放大器的反馈单元。

10. 发明申请

US20170301689A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20170301689A1
公开(公告)日：2017-10-19
申请号：US15634555
申请日：2017-06-27
申请人： Ji-Hoon CHOI , SeungHyun LIM , Sunggil KIM , HongSuk KIM , Hunhyeong LIM , Hyunjun SIM
发明人： Ji-Hoon CHOI , SeungHyun LIM , Sunggil KIM , HongSuk KIM , Hunhyeong LIM , Hyunjun SIM
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

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