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1. 发明授权

US6049867A Method and system for multi-thread switching only when a cache miss occurs at a second or higher level 失效
标题翻译：只有当第二级或更高级别发生高速缓存未命中时，多线程切换的方法和系统
公开(公告)号：US6049867A
公开(公告)日：2000-04-11
申请号：US906228
申请日：1997-08-04
申请人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
发明人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
IPC分类号： G06F9/38 , G06F9/48 , G06F12/08
CPC分类号： G06F9/4881 , G06F12/0811 , G06F12/0842 , G06F9/3851
摘要： A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.
摘要翻译：一种用于在数据处理系统中增强性能多线程操作的方法和系统，其包括处理器，主存储器存储器和至少两个级别的高速缓冲存储器。执行初始线程内的至少一条指令。此后，存储处于第一线程内的选定点的处理器的状态，终止第一线程的执行，并且仅响应于二级或更高级别的高速缓存未命中而选择执行第二线程，从而最小化处理器延迟到内存延迟。优选地保持每个线程的有效性状态，以便在高速缓存未命中被校正之前最小化返回到先前线程执行的可能性。在所有其他线程之前，对于线程的有效状态的改变，优选地，在与所有剩余线程相关联的非有效性指示的情况下，选择最不执行的线程用于执行。线程切换位也可用于选择性地禁止线程切换，其中特定线程的执行被认为是必要的。

2. 发明授权

US5651136A System and method for increasing cache efficiency through optimized data allocation 失效
标题翻译：通过优化数据分配来提高缓存效率的系统和方法
公开(公告)号：US5651136A
公开(公告)日：1997-07-22
申请号：US470315
申请日：1995-06-06
申请人： James L. Denton , Richard James Eickemeyer , Kevin Curtis Griffin , Ross Evan Johnson , Steven Raymond Kunkel , Mikko Herman Lipasti , Sandra Kay Ryan
发明人： James L. Denton , Richard James Eickemeyer , Kevin Curtis Griffin , Ross Evan Johnson , Steven Raymond Kunkel , Mikko Herman Lipasti , Sandra Kay Ryan
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F12/023
摘要： Logic for decreasing the number of cache lines dedicated to user data. When pools for allocation are selected using a dynamic storage allocation procedure, the size of a data block is compared to the size of the allocated pool. If the comparison results meet a predetermined criterion, the logic aligns the data to the beginning of a cache line and places the header in a separate cache line that may be deallocated. And if the data will fit within one-half of a cache slot in the allocated pool, then the line or lines having the header data can be re-used as the header is deallocated. Otherwise, user data blocks are placed in cache lines that are spatially local.
摘要翻译：用于减少专用于用户数据的高速缓存线数量的逻辑。当使用动态存储分配过程选择用于分配的池时，将数据块的大小与分配的池的大小进行比较。如果比较结果满足预定标准，逻辑将数据对齐到高速缓存行的开头，并将标题放置在可以被释放的单独的高速缓存行中。并且如果数据将适合分配的池中的高速缓存槽的一半，则具有报头数据的行或行可以被重新使用，因为报头被释放。否则，将用户数据块放置在空间本地的高速缓存行中。

3. 发明授权

US5924092A Computer system and method which sort array elements to optimize array modifications 失效
标题翻译：对阵列元素进行排序以优化阵列修改的计算机系统和方法
公开(公告)号：US5924092A
公开(公告)日：1999-07-13
申请号：US797760
申请日：1997-02-07
申请人： Ross Evan Johnson
发明人： Ross Evan Johnson
IPC分类号： G06F12/00 , G06F7/24 , G06F12/02 , G06F12/04 , G06F7/00
CPC分类号： G06F7/24 , Y10S707/99937 , Y10S707/99942
摘要： A sorting algorithm is applied to an array data structure to arrange array elements according to the predicted frequency by which those array elements are likely to be modified. Higher modification frequency array elements are arranged proximate the end of the array to minimize the number of array elements that will typically need to be updated in response to modification of these array elements, reserving the modifications that require more array elements to be updated to those array elements that have a lower likelihood of modification. A sorting algorithm suitable for use in memory compression arranges blocks for a given page in reverse order since data located proximate the beginning of a page has a higher probability of being modified than the data proximate the end of the page.
摘要翻译：排序算法被应用于阵列数据结构，以根据这些阵列元素可能被修改的预测频率排列阵列元素。更高的修改频率数组元素靠近阵列的末端排列，以最小化响应于这些数组元素的修改而通常需要更新的数组元素的数量，保留需要更多数组元素以更新到那些数组的修改具有较低修改可能性的元素。适用于存储器压缩的排序算法以相反的顺序排列给定页面的块，因为位于页面开头附近的数据具有比接近页面末尾的数据更高的修改概率。

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