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1. 发明申请

US20090150642A1 Indexing Page Attributes 有权
标题翻译：索引页面属性
公开(公告)号：US20090150642A1
公开(公告)日：2009-06-11
申请号：US11950518
申请日：2007-12-05
申请人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
发明人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
IPC分类号： G06F12/10
CPC分类号： G06F12/0893 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.
摘要翻译：本发明的实施例提供了用于增加由页表指定的页面属性的数量的方法和装置，同时最小化页表的大小的增加。根据本发明的实施例，属性索引位可以包括在页表内，并且可以用于确定存储在属性索引内的页面属性。另外，本发明的实施例提供了多个新的页面属性。

2. 发明授权

US06314500B1 Selective routing of data in a multi-level memory architecture based on source identification information 有权
标题翻译：基于源标识信息在多级存储器体系结构中选择性地选择数据
公开(公告)号：US06314500B1
公开(公告)日：2001-11-06
申请号：US09228314
申请日：1999-01-11
申请人： James Allen Rose
发明人： James Allen Rose
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize source identification information to selectively route data to different memory sources in a shared memory system. This permits, for example, data to be routed to only a portion of the memory sources associated with a given requester, thereby reducing the bandwidth to other memory sources and reducing overall latencies within the system. Among other possible information, the source identification information may include an identification of which memory source and/or which level of memory is providing the requested data, and/or an indication of what processor/requester and/or what type of instruction last modified the requested data.
摘要翻译：数据处理系统，电路布置，集成电路设备，程序产品和方法利用源标识信息来选择性地将数据路由到共享存储器系统中的不同存储器源。这允许例如将数据路由到仅与给定请求者相关联的一部分存储器源，从而减少对其他存储器源的带宽并减少系统内的总延迟。在其他可能的信息中，源识别信息可以包括哪个存储器源和/或哪个级别的存储器提供所请求的数据的标识，和/或什么处理器/请求者和/或上一次修改什么类型的指令的指示请求的数据。

3. 发明授权

US6049867A Method and system for multi-thread switching only when a cache miss occurs at a second or higher level 失效
标题翻译：只有当第二级或更高级别发生高速缓存未命中时，多线程切换的方法和系统
公开(公告)号：US6049867A
公开(公告)日：2000-04-11
申请号：US906228
申请日：1997-08-04
申请人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
发明人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
IPC分类号： G06F9/38 , G06F9/48 , G06F12/08
CPC分类号： G06F9/4881 , G06F12/0811 , G06F12/0842 , G06F9/3851
摘要： A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.
摘要翻译：一种用于在数据处理系统中增强性能多线程操作的方法和系统，其包括处理器，主存储器存储器和至少两个级别的高速缓冲存储器。执行初始线程内的至少一条指令。此后，存储处于第一线程内的选定点的处理器的状态，终止第一线程的执行，并且仅响应于二级或更高级别的高速缓存未命中而选择执行第二线程，从而最小化处理器延迟到内存延迟。优选地保持每个线程的有效性状态，以便在高速缓存未命中被校正之前最小化返回到先前线程执行的可能性。在所有其他线程之前，对于线程的有效状态的改变，优选地，在与所有剩余线程相关联的非有效性指示的情况下，选择最不执行的线程用于执行。线程切换位也可用于选择性地禁止线程切换，其中特定线程的执行被认为是必要的。

4. 发明授权

US08028118B2 Using an index value located on a page table to index page attributes 有权
标题翻译：使用页表上的索引值来索引页面属性
公开(公告)号：US08028118B2
公开(公告)日：2011-09-27
申请号：US11950518
申请日：2007-12-05
申请人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
发明人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
IPC分类号： G06F12/10
CPC分类号： G06F12/0893 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.
摘要翻译：本发明的实施例提供了用于增加由页表指定的页面属性的数量的方法和装置，同时最小化页表的大小的增加。根据本发明的实施例，属性索引位可以包括在页表内，并且可以用于确定存储在属性索引内的页面属性。另外，本发明的实施例提供了多个新的页面属性。

5. 发明授权

US07739477B2 Multiple page size address translation incorporating page size prediction 有权
标题翻译：多页尺寸地址转换结合页面大小预测
公开(公告)号：US07739477B2
公开(公告)日：2010-06-15
申请号：US11733520
申请日：2007-04-10
申请人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
发明人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1036 , G06F2212/652
摘要： Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.
摘要翻译：页面大小预测用于预测由存储器访问指令访问的存储器页面的页面大小，使得可以使用预测的页面大小来访问地址转换数据结构。通过这样做，地址转换数据结构可以以有效的方式支持多个页面大小，并且在关键路径中设置少量额外的电路用于地址转换，从而提高性能。

6. 发明授权

US07284112B2 Multiple page size address translation incorporating page size prediction 失效
标题翻译：多页尺寸地址转换结合页面大小预测
公开(公告)号：US07284112B2
公开(公告)日：2007-10-16
申请号：US11035556
申请日：2005-01-14
申请人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
发明人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/1036 , G06F2212/652
摘要： Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.
摘要翻译：页面大小预测用于预测由存储器访问指令访问的存储器页面的页面大小，使得可以使用预测的页面大小来访问地址转换数据结构。通过这样做，地址转换数据结构可以以有效的方式支持多个页面大小，并且在关键路径中设置少量额外的电路用于地址转换，从而提高性能。

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