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1. 发明授权

US06232844B1 Controlled orthogonal current oscillator with ranging 有权
标题翻译：带有测距的受控正交电流振荡器
公开(公告)号：US06232844B1
公开(公告)日：2001-05-15
申请号：US09322738
申请日：1999-05-28
申请人： Ronald F. Talaga, Jr.
发明人： Ronald F. Talaga, Jr.
IPC分类号： H03B524
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1228
摘要： An adjustable frequency oscillator with a wide tuning range which can be voltage or current controlled. A maximum tuning per feedback current is obtained by phase shifting a feedback signal by approximately 90 degrees with respect to the oscillating output signal, which is internally generated by the adjustable frequency oscillator. Over the frequency range of operation, the oscillation frequency of the oscillating output signal is linearly controllable. The adjustable frequency oscillator is also implemented as a ring oscillator and/or an oscillator with ranging.
摘要翻译：具有宽调谐范围的可调频率振荡器，可以进行电压或电流控制。通过将反馈信号相对于由可调频振荡器在内部产生的振荡输出信号相移大约90度来获得每反馈电流的最大调谐。在工作频率范围内，振荡输出信号的振荡频率是线性可控的。可调谐振荡器也被实现为环形振荡器和/或具有测距的振荡器。

2. 发明授权

US06052006A Current mirror triggered power-on-reset circuit 失效
标题翻译：电流镜触发上电复位电路
公开(公告)号：US06052006A
公开(公告)日：2000-04-18
申请号：US85444
申请日：1998-05-27
申请人： Ronald F. Talaga, Jr. , Russell Hershbarger
发明人： Ronald F. Talaga, Jr. , Russell Hershbarger
IPC分类号： H03K17/22 , H03L7/00
CPC分类号： H03K17/223
摘要： The present disclosure encompasses the use of a current mirror to control the trip point for a power-on-reset circuit. The current mirror is designed to turn on at a multiple of a transistor threshold voltage V.sub.t. The power-on-reset circuit asserts a power-on signal in response to mirror current provided by the current mirror when the supply voltage ramps up above the V.sub.t multiple. Since the transistor threshold voltage may be tightly controlled during the fabrication process, the trip point for the power-on-reset circuit may be precisely and accurately adjusted to match the minimum operating supply voltage level specified for an integrated circuit device such as a microprocessor. Also, a feedback path may be provided in the power-on-reset circuit to turn off the current mirror once the power-on signal is asserted so that there is no current draw in the power-on-circuit for static conditions. The lack of current draw at static power conditions prevents unnecessary power consumption and false stuck-at faults during I.sub.ddq testing.
摘要翻译：本公开包括使用电流镜来控制上电复位电路的跳变点。电流镜被设计成以晶体管阈值电压Vt的倍数导通。当电源电压上升到Vt以上时，上电复位电路响应于由电流镜提供的镜电流来断言上电信号多。由于晶体管阈值电压可以在制造过程中被严格控制，因此可以精确地和准确地调整上电复位电路的跳变点，以匹配对诸如微处理器的集成电路器件指定的最小工作电源电压电平。此外，在通电复位电路中可以提供反馈路径，以便在电源接通信号被断言时关闭电流镜，使得在静态条件下的电源电路中不存在电流消耗。在静态功率条件下缺少电流消除可防止Iddq测试期间不必要的功耗和错误的卡住故障。

3. 发明授权

US6014048A Clock generator with multiple feedback paths including a delay locked loop path 失效
标题翻译：具有多个反馈路径的时钟发生器，包括延迟锁定环路径
公开(公告)号：US6014048A
公开(公告)日：2000-01-11
申请号：US085509
申请日：1998-05-27
申请人： Ronald F. Talaga, Jr. , Russell Hershbarger , James M. Buchanan
发明人： Ronald F. Talaga, Jr. , Russell Hershbarger , James M. Buchanan
IPC分类号： G06F1/10 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/18
CPC分类号： G06F1/10 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/18
摘要： The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.
摘要翻译：本发明包括在集成电路设备的时钟源中使用多个反馈路径来维持对外部时钟的相位锁定。本发明进一步设想，从内部时钟分配路径和近似时钟分配路径的延迟的匹配路径提供反馈路径。匹配路径可以包括延迟锁定环路。在正常操作中使用时钟分配路径的反馈，当禁止内部时钟分配路径时，使用来自匹配路径的反馈。本发明的时钟源还可以实现电源管理功能。

4. 发明授权

US5963059A Phase frequency detector having reduced blind spot 失效
标题翻译：相位频率检测器具有减少的盲点
公开(公告)号：US5963059A
公开(公告)日：1999-10-05
申请号：US993340
申请日：1997-12-19
申请人： Hamid Partovi , Ronald F. Talaga, Jr.
发明人： Hamid Partovi , Ronald F. Talaga, Jr.
IPC分类号： H03D13/00 , H03L7/089 , H03D3/20
CPC分类号： H03D13/004 , H03L7/0891
摘要： A phase-frequency detector provides a decreased blind spot near 360.degree. of phase error and a resulting increased phase error detection range. In one embodiment, the phase-frequency detector includes two latches that are set in response to the detection of positive transitions in respective input clock signals. A reset controller resets both latches when they both get set. The duration and sequence of the latch states are thereby indicative of phase errors between the input clock signals. Two edge-triggered pulse generators provide a sustained indication of a detected positive transition in the respective input clock signals. When the time duration of the sustained indications is set equal to the reset time required by the latches and reset controller, the blind spot of the phase-frequency detector is largely eliminated.
摘要翻译：相位检测器在相位误差360°附近提供减少的盲点，从而提高相位误差检测范围。在一个实施例中，相位 - 频率检测器包括响应于各个输入时钟信号中的正跳变的检测而设置的两个锁存器。复位控制器在两个锁存器都被置位时复位。因此锁存状态的持续时间和序列表示输入时钟信号之间的相位误差。两个边沿触发脉冲发生器提供在各个输入时钟信号中检测到的正转换的持续指示。当持续指示的持续时间设置为等于锁存器和复位控制器所需的复位时间时，相位频率检测器的盲点被大大消除。

5. 发明授权

US06996202B2 Multiple channel adaptive data recovery system 有权
公开(公告)号：US06996202B2
公开(公告)日：2006-02-07
申请号：US10266383
申请日：2002-10-07
申请人： Gary D. McCormack , Ronald F. Talaga, Jr.
发明人： Gary D. McCormack , Ronald F. Talaga, Jr.
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/0037 , H04L7/0334 , H04L25/0262 , H04L25/063
摘要： A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

6. 发明授权

US06178213B1 Adaptive data recovery system and methods 有权
标题翻译：自适应数据恢复系统和方法
公开(公告)号：US06178213B1
公开(公告)日：2001-01-23
申请号：US09139252
申请日：1998-08-25
申请人： Gary D. McCormack , Ronald F. Talaga, Jr. , Ian A. Kyles , Angus J. McCamant
发明人： Gary D. McCormack , Ronald F. Talaga, Jr. , Ian A. Kyles , Angus J. McCamant
IPC分类号： H04L700
CPC分类号： H04L25/063 , H04L7/0037 , H04L7/033 , H04L7/0334
摘要： A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.
摘要翻译：具有可调取样和信号比较级别的微处理器控制的数据恢复单元。数据恢复单元包括数据通道和监视通道。监视器通道以不同的方式对输入的数据流进行采样。监视通道中采样的结果用于调整数据通道中信号的采样和比较。在一个实施例中，数据恢复单元包括基于PLL的时钟恢复单元，在另一实施例中，时钟信号由微处理器导出。

7. 发明授权

US06463109B1 Multiple channel adaptive data recovery system 有权
标题翻译：多通道自适应数据恢复系统
公开(公告)号：US06463109B1
公开(公告)日：2002-10-08
申请号：US09531277
申请日：2000-03-20
申请人： Gary D. McCormack , Ronald F. Talaga, Jr.
发明人： Gary D. McCormack , Ronald F. Talaga, Jr.
IPC分类号： H04L700
CPC分类号： H04L7/033 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/0037 , H04L7/0334 , H04L25/0262 , H04L25/063
摘要： A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.
摘要翻译：具有可调取样和信号比较级别的微处理器控制的数据恢复单元。数据恢复单元包括数据通道和监视通道。监视器通道以不同的方式对输入的数据流进行采样。监视通道中采样的结果用于调整数据通道中信号的采样和比较。在一个实施例中，数据恢复单元包括基于PLL的时钟恢复单元，在另一实施例中，时钟信号由微处理器导出。

8. 发明授权

US5942921A Differential comparator with an extended input range 失效
标题翻译：差分比较器具有扩展输入范围
公开(公告)号：US5942921A
公开(公告)日：1999-08-24
申请号：US994144
申请日：1997-12-19
申请人： Ronald F. Talaga, Jr.
发明人： Ronald F. Talaga, Jr.
IPC分类号： H03K5/24 , H03K5/22
CPC分类号： H03K5/2481
摘要： A differential comparator is provided with an extended input range. In one embodiment, a differential amplifier is provided with a differential input buffer that allows for differential detection even with input voltage signal levels that extend two or more volts beyond the power supply voltage. A first transistor and a first resistor coupled in series are coupled in parallel with a second transistor and a second series resistor. The transistor drain terminals are both coupled to the power supply voltage, and a current source draws current from the common node of the resistors. Input voltages are supplied to the gates of the transistors, and the differential output voltages are provided from the transistor source terminals. A differential amplifier receives the differential output voltages and provides a single output voltage.
摘要翻译：差分比较器具有扩展输入范围。在一个实施例中，差分放大器设置有差分输入缓冲器，其允许即使在延伸超过电源电压两个或更多伏的输入电压信号电平的情况下进行差分检测。串联耦合的第一晶体管和第一电阻器与第二晶体管和第二串联电阻器并联耦合。晶体管漏极端子都耦合到电源电压，电流源从电阻器的公共节点吸取电流。输入电压被提供给晶体管的栅极，并且差分输出电压由晶体管源极端子提供。差分放大器接收差分输出电压并提供单个输出电压。

9. 发明授权

US5926042A Precision clock frequency detector having reduced supply voltage dependence 失效
标题翻译：精密时钟频率检测器具有降低的电源电压依赖性
公开(公告)号：US5926042A
公开(公告)日：1999-07-20
申请号：US994137
申请日：1997-12-19
申请人： Ronald F. Talaga, Jr.
发明人： Ronald F. Talaga, Jr.
IPC分类号： G01R23/00 , H03K5/153 , H03K5/19 , G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： G01R23/005 , H03K5/153 , H03K5/19
摘要： A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted. When the clock signal is de-asserted, the capacitor is allowed to charge, and an op-amp detects when the capacitor voltage exceeds a reference voltage and asserts an output signal. The reference voltage is also provided using a current source, so the transition delay is independent of changes in the power supply voltage. The clock frequency detector provided herein has a high precision with respect to process variation. A consistent frequency detection performance is achieved which is insensitive to changes in power supply voltage. This advantageously provides microprocessors with an added degree of reliability as higher circuit densities and lower supply voltages are pursued.
摘要翻译：提供了具有对电源变化不敏感的精确跳闸频率的时钟频率检测器。在一个实施例中，时钟频率检测器采用电流源以恒定速率放电电容器和门控电流源，以频率依赖率对电容器充电。如果充电速率超过放电速率，电容器将充电并输出一个输出信号。门控电流源由边沿触发脉冲发生器控制，边沿触发脉冲发生器响应于输入时钟信号中的边沿产生精确宽度的脉冲。为了产生这些脉冲，脉冲发生器产生具有延迟转换的反相时钟信号，并将该信号与时钟信号组合。使用由电流源充电的电容器产生延迟转换。电容器设有分流晶体管，每当时钟信号被断言时，该晶体管从电容器中消耗电荷。当时钟信号被取消置位时，允许电容器充电，并且运算放大器检测电容器电压何时超过参考电压并断言输出信号。参考电压也使用电流源提供，因此转换延迟与电源电压的变化无关。这里提供的时钟频率检测器具有相对于工艺变化的高精度。实现了对电源电压变化不敏感的一致的频率检测性能。这有利地为微处理器提供了更高的可靠性，因为追求更高的电路密度和更低的电源电压。

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