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1. 发明授权

US4242650A Active variable equalizer 失效
标题翻译：主动变量均衡器
公开(公告)号：US4242650A
公开(公告)日：1980-12-30
申请号：US959451
申请日：1978-11-13
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H04B3/14
CPC分类号： H04B3/145
摘要： An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.A circuit interconnects with input and output terminals for combining input and output signals into an intermediate signal having a magnitude equal to a weighted sum of the input and output signals. A frequency dependent circuit responds to the intermediate signal for producing a frequency dependent signal that is combined with the input signal to generate the output signal.
摘要翻译：布置有源可变均衡器以提供波特型可变均衡器特性而不需要电感器。随着均衡量的变化，均衡形状保持不变。该均衡器使用加法前馈和负反馈的串联布置来实现所提到的均衡形状。电路与输入和输出端相互连接，用于将输入和输出信号组合成具有等于输入和输出信号的加权和的幅度的中间信号。频率相关电路响应中间信号以产生与输入信号组合的频率相关信号以产生输出信号。

2. 发明授权

US06333799B1 Hybrid wavelength-interchanging cross-connect 失效
标题翻译：混合波长交换交叉连接
公开(公告)号：US06333799B1
公开(公告)日：2001-12-25
申请号：US09003117
申请日：1998-01-06
申请人： Krishna Bala , Gee-Kung Chang , Robert R. Cordell
发明人： Krishna Bala , Gee-Kung Chang , Robert R. Cordell
IPC分类号： H04J1402
CPC分类号： H04Q11/0001 , H04J14/0206 , H04J14/0212 , H04J14/0217 , H04J14/022 , H04Q11/0005 , H04Q11/0071 , H04Q2011/0016 , H04Q2011/0039 , H04Q2011/0041 , H04Q2011/005
摘要： A wavelength-interchanging cross-connect for a wavelength-division multiplexing (WDM) optical communication system including both transparent optical paths and opaque paths through an electronic switching network, such as a high-speed digital cross-connect switch (DCS), including matching opto-electronic conversions of the data signal. All-optical switching is performed on the input and output sides, for example, by mechanically actuated fiber switches. The DCS, receiving optical inputs from the input optical switches and providing optical outputs to the output optical switches, performs switching in the electrical domain and can perform wavelength conversion of the signals passing through it. The DCS also provides for access to electrical add/drop lines for interfacing to a client. The transparent optical path, which can be either direct or through an optical switch, transfers a signal without regard to its format from the input to the output of the switching system. An algorithm is available for setting up the required connection through the different components.
摘要翻译：一种用于波分复用（WDM）光通信系统的波长交换交叉连接，包括通过诸如高速数字交叉连接交换机（DCS）的电子交换网络的透明光路和不透明路径，包括匹配光电转换的数据信号。全光开关在输入和输出侧进行，例如通过机械驱动的光纤开关进行。从输入光开关接收光输入并向输出光开关提供光输出的DCS在电域中执行切换，并且可以对通过它的信号进行波长转换。 DCS还提供访问用于与客户端连接的电气添加/关闭线路。可以是直接的或通过光学开关的透明光路传送信号而不考虑其从输入到切换系统的输出的格式。一种算法可用于通过不同的组件设置所需的连接。

3. 发明授权

US07130030B2 System and method for rapidly achieving optimum dispersion in optical transmission systems 有权
标题翻译：快速实现光传输系统最佳色散的系统和方法
公开(公告)号：US07130030B2
公开(公告)日：2006-10-31
申请号：US10677193
申请日：2003-10-02
申请人： Carl R. Davidson , Robert R. Cordell , Yi Cai , Hongbin Zhang
发明人： Carl R. Davidson , Robert R. Cordell , Yi Cai , Hongbin Zhang
IPC分类号： G01N21/00
CPC分类号： H04B10/25133 , H04B10/07951 , H04B10/2513 , H04B10/697 , H04J14/02
摘要： A system and method for optimizing dispersion in an optical transmission line is provided. The system and method comprise measuring the amplitude of a d.c. voltage component of a synchronously demodulated data signal of at least one wavelength channel by an in-phase carrier at the baud frequency of the wavelength channel. In an alternative embodiment, the system and method comprise measuring the IF amplitude of the resulting a.c. signal of a data signal of the at least one wavelength channel comprising a received RZ signal mixed with a local oscillator, whose frequency differs from the wavelength channel baud by a relatively small amount, somewhere on the order of about 100 kHz.
摘要翻译：提供了一种用于优化光传输线中的色散的系统和方法。该系统和方法包括测量直流的振幅。通过同相载波在波长信道的波特率下的至少一个波长信道的同步解调数据信号的电压分量。在替代实施例中，系统和方法包括测量所产生的交流电的IF幅度。所述至少一个波长信道的数据信号的信号包括与本地振荡器混合的接收到的RZ信号，所述本地振荡器的频率与波长信道波特相差相对较小的量，约为100kHz的数量级。

4. 发明授权

US5367520A Method and system for routing cells in an ATM switch 失效
标题翻译：用于在ATM交换机中路由单元的方法和系统
公开(公告)号：US5367520A
公开(公告)日：1994-11-22
申请号：US981715
申请日：1992-11-25
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/3081 , H04Q11/0478 , H04L2012/5679 , H04L2012/5681
摘要： A method and a system for routing cells in an ATM switch. The switch which is input buffered, employs a multiplicity of crosspoint switch planes operating simultaneously in parallel, and whose outputs are combined by an output-buffered second stage. A traffic controlling or path assignment switching stage disposed before the crosspoint switch planes improves performance in the presence of correlated traffic. The switching stage may either control the traffic randomly or adaptively. Input concentration and output expansion functions within the switch are also disclosed. The use of an "unfair" or a predictable preference contention resolution device (CRD) in each of the crosspoint switch planes is possible in another embodiment of the invention. Advantages of the method and system include linear growth with large N in the size and complexity of both the switching circuits and the contention resolution circuits. Switch performance tends to gracefully degrade with failures in switch planes and contention resolution devices. Dense, low-cost memory with simple FIFO addressing schemes can be used to realize both the input and output buffered stages.
摘要翻译：一种用于在ATM交换机中路由单元的方法和系统。输入缓冲的开关采用并行运行的多个交叉点开关平面，其输出由输出缓冲的第二级组合。布置在交叉点开关平面之前的交通控制或路径分配切换阶段在存在相关业务的情况下提高性能。切换阶段可以随机地或自适应地控制流量。还公开了开关内的输入浓度和输出扩展功能。在本发明的另一实施例中，在每个交叉点开关平面中使用“不公平”或可预测的偏好争用解决装置（CRD）是可能的。该方法和系统的优点包括在开关电路和争用解决电路两者的尺寸和复杂性方面具有大N的线性增长。交换机性能往往随着交换机平面和争用解决设备的故障而正常地降级。使用简单的FIFO寻址方案的密集低成本内存可用于实现输入和输出缓冲级。

5. 发明授权

US4773085A Phase and frequency detector circuits 失效
标题翻译：相位和频率检测电路
公开(公告)号：US4773085A
公开(公告)日：1988-09-20
申请号：US62494
申请日：1987-06-12
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H03L7/089 , H03L7/091 , H04L7/033 , H03D3/24
CPC分类号： H03L7/091 , H03L7/0891 , H04L7/033
摘要： A Phase/Frequency Locked Loop comprises a controllable oscillator which is phase locked with the clock of an incoming non-return-to-zero digital data signal. The controllable oscillator may be a voltage-controlled oscillator (VCO) or may be purely digital. The circuitry includes a novel digital phase and frequency detector which detects both frequency and phase error by sampling the incoming data stream at multiple phases of the output of the VCO (or the digital equivalent thereof). One of two binary disagreement signals are produced depending on the sense of the phase error. During periods of frequency error, the circuit automatically selects the proper type of disagreement signal (the leading-edge disagreement) required to achieve frequency lock.
摘要翻译：相位/频率锁定环包括可控振荡器，其与输入的非归零数字数据信号的时钟锁相。可控振荡器可以是压控振荡器（VCO），或者可以是纯数字的。该电路包括一个新颖的数字相位和频率检测器，通过在VCO的输出的多个相位（或其数字等价物）上对输入数据流进行采样来检测频率和相位误差。根据相位误差的感觉产生两个二进制不一致信号之一。在频率误差期间，电路自动选择实现频率锁定所需的正确类型的不一致信号（前沿不一致）。

6. 发明授权

US4756011A Digital phase aligner 失效
标题翻译：数字相位对准器
公开(公告)号：US4756011A
公开(公告)日：1988-07-05
申请号：US946323
申请日：1986-12-24
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0338
摘要： This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0.degree.) and anti-phase (180.degree.) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.
摘要翻译：该电路阶段将相变输入数据流与本地时钟对准。输入数据流在四个正交点进行采样，并将这些采样应用于Ex-Or门，以产生四个不一致信号，指示在任何一对样本之间是否发生了从二进制0到1的转换，反之亦然。同相（0°）和反相（180°）样品连续装载到不同但相似的移位寄存器中，其抽头为输入数据流的早期版本或更高版本在0°或180°提供输出 DEG。控制电路分析不一致信号，并提供控制信号，确定哪个移位寄存器抽头连接到对准器输出端。该电路可以校正输入数据和本地时钟之间的相位滑差，最多可以加上或多于几个时隙。

7. 发明授权

US4219788A Active variable equalizer 失效
标题翻译：主动变量均衡器
公开(公告)号：US4219788A
公开(公告)日：1980-08-26
申请号：US954306
申请日：1978-10-24
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H04B3/14 , H03H7/14
CPC分类号： H04B3/141
摘要： An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.
摘要翻译：布置有源可变均衡器以提供波特型可变均衡器特性而不需要电感器。随着均衡量的变化，均衡形状保持不变。该均衡器使用加法前馈和负反馈的串联布置来实现所提到的均衡形状。

8. 发明授权

US07256877B2 System and method for rapidly achieving optimum dispersion in optical transmission systems 失效
标题翻译：快速实现光传输系统最佳色散的系统和方法
公开(公告)号：US07256877B2
公开(公告)日：2007-08-14
申请号：US11340880
申请日：2006-01-26
申请人： Robert R. Cordell , Carl R. Davidson , Yi Cai , Hongbin Zhang
发明人： Robert R. Cordell , Carl R. Davidson , Yi Cai , Hongbin Zhang
IPC分类号： G01N21/00
CPC分类号： H04B10/25133 , H04B10/07951 , H04B10/2513 , H04B10/697 , H04J14/02
摘要： A system and method for optimizing dispersion in an optical transmission line is provided. The system and method comprise measuring the amplitude of a d.c. voltage component of a synchronously demodulated data signal of at least one wavelength channel by an in-phase carrier at the baud frequency of the wavelength channel. In an alternative embodiment, the system and method comprise measuring the IF amplitude of the resulting a.c. signal of a data signal of the at least one wavelength channel comprising a received RZ signal mixed with a local oscillator, whose frequency differs from the wavelength channel baud by a relatively small amount, somewhere on the order of about 100 kHz.
摘要翻译：提供了一种用于优化光传输线中的色散的系统和方法。该系统和方法包括测量直流的振幅。通过同相载波在波长信道的波特率下的至少一个波长信道的同步解调数据信号的电压分量。在替代实施例中，系统和方法包括测量所产生的交流电的IF幅度。所述至少一个波长信道的数据信号的信号包括与本地振荡器混合的接收到的RZ信号，所述本地振荡器的频率与波长信道波特相差相对较小的量，约为100kHz的数量级。

9. 发明授权

US5055841A High-speed feedforward variable word length decoder 失效
标题翻译：高速前馈可变字长解码器
公开(公告)号：US5055841A
公开(公告)日：1991-10-08
申请号：US649655
申请日：1991-02-01
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H03M7/42
CPC分类号： H03M7/425
摘要： A variable word length (VWL) decoder is disclosed in which an input bit stream of variable length words is input to a programmable logic array (PLA) (305) through an input shift register (302). The data association input plane (306) of the PLA compares the sequence of input bits in the register with all the possible variable length words. When a match is made, the PLA's length output plan (307) produces an output word representing the length of the detected variable length word and the PLA's word output plan (308) produces the fixed length word corresponding to the input VWL word. This fixed length word is input to a latch which is controlled by a downcounter (311). The length word is loaded into this downcounter, which decrements its count as the input bits are shifted through the register. Only when its count reaches zero have all bits of the previous variable length word been clocked through the shift register. Therefore, only on the count of zero does the output of the word output plane represent a fixed length word that properly corresponds to a valid VWL input word. Thus, only on the count of zero is the latch enabled to transfer to its output the word then at the output of the word output plane. The feedforward only architecture of the VWL decoder does not require any information regarding the decoded word length to be fed back to the input. This architecture is therfore not limited by speed constraints that would otherwise exist if the length of each decoded word needed to be fed back to the input before the next word could be decoded.
摘要翻译：公开了一种可变字长（VWL）解码器，其中可变长度字的输入比特流通过输入移位寄存器（302）输入到可编程逻辑阵列（PLA）（305）。 PLA的数据关联输入平面（306）将寄存器中的输入位序列与所有可能的可变长度字进行比较。当匹配时，PLA的长度输出计划（307）产生表示检测到的可变长度字长度的输出字，PLA的字输出计划（308）产生对应于输入VWL字的固定长度字。这个固定长度的字被输入到由下行计数器（311）控制的锁存器。长度字被加载到这个下位机中，当输入位通过寄存器移位时，它减少其计数。只有当其计数达到零时，前一可变长度字的所有位都通过移位寄存器计时。因此，只有在零计数时，字输出平面的输出表示一个固定长度的字才能正确对应于有效的VWL输入字。因此，只有在计数为零时，锁存器能够在字输出平面的输出端传输到其输出字。 VWL解码器的仅前馈架构不需要关于将被解码的字长反馈到输入的任何信息。如果在下一个字可以被解码之前需要将每个解码字的长度反馈到输入的情况下，这种结构不受速度约束的限制。

10. 发明授权

US4821296A Digital phase aligner with outrigger sampling 失效
标题翻译：带外伸支架采样的数字相位对准器
公开(公告)号：US4821296A
公开(公告)日：1989-04-11
申请号：US89609
申请日：1987-08-26
申请人： Robert R. Cordell
发明人： Robert R. Cordell
IPC分类号： H04L7/033 , H03D3/24
CPC分类号： H04L7/0338
摘要： The circuit phase aligns a phase-varying input data stream with a local clock. The data stream is sampled at the 0.degree. and 180.degree. phases of the local clock. Two pairs of outrigger samples which closely bracket the aforementioned primary samples are also obtained by the sextet sampler. Adjacent pairs of the six samples are applied to Ex-Or gates to yield disagreement signals which indicate the locations of data transitions relative to the samples. The primary samples (0.degree. and 180.degree.) are serially loaded into different halves of a biphase register, the taps of which provide the output with differently delayed versions of the input data at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals to a counter which determines which of the biphase register taps is connected to the output. The output is a replica of the input which is synchronized with the local clock.
摘要翻译：电路阶段将相变输入数据流与本地时钟对准。数据流在本地时钟的0°和180°阶段进行采样。通过六分选择器也可以获得两对紧密包围上述初级样品的外伸支架样本。将六个样本的相邻对应用于Ex-Or门以产生指示相对于样本的数据转变的位置的不一致信号。主要样品（0°和180°）串联装载到双相寄存器的不同的两半中，其中的抽头在0°或180°时为输入数据提供不同延迟的输入数据。控制电路分析不一致信号，并向计数器提供控制信号，该计数器确定双相寄存器抽头中的哪一个连接到输出端。输出是与本地时钟同步的输入的副本。

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