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1. 发明授权

US09495169B2 Predicate trace compression 有权
标题翻译：谓词跟踪压缩
公开(公告)号：US09495169B2
公开(公告)日：2016-11-15
申请号：US13449411
申请日：2012-04-18
申请人： Robert N. Ehrlich , Petru Lauric , Robert A. McGowan
发明人： Robert N. Ehrlich , Petru Lauric , Robert A. McGowan
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3853 , G06F9/30072
摘要： A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.
摘要翻译：一种程序跟踪数据压缩机制，其中以允许通过将跟踪数据与跟踪数据相关联的指令执行完全重建的方式实时地跟踪包括多个非分支条件指令的可变长度执行集（VLES）的执行跟踪二进制代码。

2. 发明授权

US08572323B2 Cache result register for quick cache information lookup 有权
标题翻译：缓存结果寄存器用于快速缓存信息查找
公开(公告)号：US08572323B2
公开(公告)日：2013-10-29
申请号：US12982856
申请日：2010-12-30
申请人： Robert Ehrlich , Kevin C. Heuer , Robert A. McGowan
发明人： Robert Ehrlich , Kevin C. Heuer , Robert A. McGowan
IPC分类号： G06F12/08
CPC分类号： G06F11/362 , G06F12/0897
摘要： Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache's CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus.
摘要翻译：高速缓存结果寄存器（CRR）配置设备内存分层结构中的每个级别的高速缓存。高速缓存通过外围总线耦合到调试器接口。设备处于调试模式，调试器将虚拟事务的事务地址（TA）转发给设备。在接收到TA时，设备处理器通过系统总线将TA转发到存储器层次结构，以在每个级别的缓存内启动地址查找操作。对于TA命中的每个高速缓存，高速缓存控制器（调试）逻辑使用Hit，Way和Index值更新缓存的CRR，从而标识存储相应指令/数据的特定高速缓存内的物理存储位置。调试器通过外围总线的直接请求检索有关命中/未命中状态，物理存储位置和/或数据副本的信息。

3. 发明申请

US20120297260A1 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY 有权
标题翻译：屏蔽SCAN链拓扑变化的扫描链测试的影响
公开(公告)号：US20120297260A1
公开(公告)日：2012-11-22
申请号：US13564339
申请日：2012-08-01
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

4. 发明授权

US08261143B2 Select signal and component override signal controlling multiplexing TDI/TDO 有权
标题翻译：选择信号和分量覆盖信号控制复用TDI / TDO
公开(公告)号：US08261143B2
公开(公告)日：2012-09-04
申请号：US12116471
申请日：2008-05-07
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

5. 发明申请

US20090013226A1 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY 有权
标题翻译：屏蔽SCAN链拓扑变化的扫描链测试的影响
公开(公告)号：US20090013226A1
公开(公告)日：2009-01-08
申请号：US12116471
申请日：2008-05-07
申请人： Gary L. SWOBODA , Robert A. MCGOWAN
发明人： Gary L. SWOBODA , Robert A. MCGOWAN
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

6. 发明授权

US07315808B2 Correlating on-chip data processor trace information for export 有权
标题翻译：相关的片上数据处理器跟踪信息进行导出
公开(公告)号：US07315808B2
公开(公告)日：2008-01-01
申请号：US09943599
申请日：2001-08-30
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455 , G06F11/00
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.
摘要翻译：在产生数据处理器仿真信息时，在程序计数器跟踪流中提供由数据处理器使用的程序计数器值，并将同步标记插入到程序计数器跟踪流中。还提供指示由数据处理器执行的数据处理操作的跟踪信息，并且识别与数据处理操作相对应的程序计数器值。在该识别中，相应的程序计数器值被表示为指示程序计数器跟踪流中的程序计数器值的数量的偏移量，通过该偏移量，相应的程序计数器值从程序计数器跟踪流中的同步标记偏移。

7. 发明授权

US08181067B2 Apparatus and method for test and debug of a processor/core having advanced power management 有权
标题翻译：具有高级电源管理的处理器/内核的测试和调试的装置和方法
公开(公告)号：US08181067B2
公开(公告)日：2012-05-15
申请号：US12321248
申请日：2009-01-20
申请人： Robert A. McGowan
发明人： Robert A. McGowan
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.
摘要翻译：接口单元被提供在涉及多个处理器核心的JTAG测试和调试过程中。接口单元包括TAP单元。开关单元耦合到接口单元，并且开关单元耦合到多个处理器/核中的每一个。当处理器/内核具有先进的电源管理系统时，睡眠抑制信号可以应用于处理器/核心状态机，以防止状态机进入较低功率状态。可以测试处理器/内核的参数，以确定何时可以实现测试和调试过程。当（power）参数为低电平以允许测试和调试时，测试和调试单元可以提供一个命令，强制状态机进入可以实现测试和调试过程的状态。

8. 发明授权

US07558984B2 Apparatus and method for test and debug of a processor/core having advanced power management 有权
公开(公告)号：US07558984B2
公开(公告)日：2009-07-07
申请号：US11411381
申请日：2006-04-26
申请人： Robert A. McGowan
发明人： Robert A. McGowan
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

9. 发明授权

US07536597B2 Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores 有权
标题翻译：用于在多个处理器/核心的测试和调试过程期间控制功率，时钟和复位的装置和方法
公开(公告)号：US07536597B2
公开(公告)日：2009-05-19
申请号：US11411683
申请日：2006-04-26
申请人： Robert A. McGowan
发明人： Robert A. McGowan
IPC分类号： G06F11/00
CPC分类号： G06F11/2242 , G06F11/2236 , G06F11/261
摘要： An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.
摘要翻译：提供接口单元，用于与涉及多个处理器核心的JTAG测试和调试过程一起使用。接口单元设置有可将测试和调试命令转换为控制信号的逻辑单元。控制信号被施加到耦合到处理器/核的电源状态机。因此可以控制功率状态机的状态，并因此控制相关处理器/核心的参数，即处理器/核心的功率和时钟参数。此外，逻辑单元可以产生用于激活开关的控制信号，可控地选择性地将TRST信号和TMS信号施加到处理器/核的TAP单元的开关。该功能允许每个处理器/核心的TAP单元同步。

10. 发明授权

US06985848B2 Obtaining and exporting on-chip data processor trace and timing information 有权
标题翻译：获取和导出片上数据处理器跟踪和时序信息
公开(公告)号：US06985848B2
公开(公告)日：2006-01-10
申请号：US09798561
申请日：2001-03-02
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.
摘要翻译：位于集成电路（14）外部的仿真控制器（12）可以被提供有指示集成电路的内部时钟的操作的定时信息，其驱动集成电路的内部数据处理活动。响应于内部时钟的每个周期，产生相应的数字位以表示内部时钟周期，并且以与内部时钟的时钟速率不同的输出时钟速率将数字位输出到仿真控制器。

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