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1. 发明授权

US06985848B2 Obtaining and exporting on-chip data processor trace and timing information 有权
标题翻译：获取和导出片上数据处理器跟踪和时序信息
公开(公告)号：US06985848B2
公开(公告)日：2006-01-10
申请号：US09798561
申请日：2001-03-02
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.
摘要翻译：位于集成电路（14）外部的仿真控制器（12）可以被提供有指示集成电路的内部时钟的操作的定时信息，其驱动集成电路的内部数据处理活动。响应于内部时钟的每个周期，产生相应的数字位以表示内部时钟周期，并且以与内部时钟的时钟速率不同的输出时钟速率将数字位输出到仿真控制器。

2. 发明授权

US07043418B2 Synchronizing on-chip data processor trace and timing information for export 有权
标题翻译：同步片上数据处理器跟踪和定时信息进行导出
公开(公告)号：US07043418B2
公开(公告)日：2006-05-09
申请号：US09943598
申请日：2001-08-30
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.
摘要翻译：可以提供指示数据处理器的内部操作的仿真信息供数据处理器外部的装置使用。提供指示由数据处理器执行的数据处理操作的仿真跟踪信息流。还提供了指示数据处理器用于执行数据处理操作的时钟的操作的定时信息流。跟踪流和定时流在其中插入了指示跟踪信息和定时信息之间的时间关系的信息。

3. 发明申请

US20120297260A1 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY 有权
标题翻译：屏蔽SCAN链拓扑变化的扫描链测试的影响
公开(公告)号：US20120297260A1
公开(公告)日：2012-11-22
申请号：US13564339
申请日：2012-08-01
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

4. 发明授权

US08261143B2 Select signal and component override signal controlling multiplexing TDI/TDO 有权
标题翻译：选择信号和分量覆盖信号控制复用TDI / TDO
公开(公告)号：US08261143B2
公开(公告)日：2012-09-04
申请号：US12116471
申请日：2008-05-07
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

5. 发明授权

US07315808B2 Correlating on-chip data processor trace information for export 有权
标题翻译：相关的片上数据处理器跟踪信息进行导出
公开(公告)号：US07315808B2
公开(公告)日：2008-01-01
申请号：US09943599
申请日：2001-08-30
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455 , G06F11/00
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.
摘要翻译：在产生数据处理器仿真信息时，在程序计数器跟踪流中提供由数据处理器使用的程序计数器值，并将同步标记插入到程序计数器跟踪流中。还提供指示由数据处理器执行的数据处理操作的跟踪信息，并且识别与数据处理操作相对应的程序计数器值。在该识别中，相应的程序计数器值被表示为指示程序计数器跟踪流中的程序计数器值的数量的偏移量，通过该偏移量，相应的程序计数器值从程序计数器跟踪流中的同步标记偏移。

6. 发明申请

US20090216521A1 Emulation export sequence with distrubuted control 审中-公开
标题翻译：仿真出口顺序与分散控制
公开(公告)号：US20090216521A1
公开(公告)日：2009-08-27
申请号：US12381273
申请日：2009-03-10
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y10S370/914
摘要： Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.
摘要翻译：通过将仿真信息配置到信息块中，从数据处理器输出包括仿真控制信息和仿真数据的仿真信息，并从数据处理器输出信息块序列。序列的一些信息块具有不同于序列的其他块中的仿真控制信息和仿真数据的相对比例的仿真控制信息和仿真数据的相对比例。

7. 发明授权

US08359502B2 TDI multiplexer gating controlled by override selection logic 有权
标题翻译： TDI多路复用器门控由覆盖选择逻辑控制
公开(公告)号：US08359502B2
公开(公告)日：2013-01-22
申请号：US13564339
申请日：2012-08-01
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/31713 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318538 , G01R31/318544 , G01R31/318555 , G01R31/318572 , G01R31/318597 , G06F11/2236
摘要： A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
摘要翻译：系统包括多个组件，耦合到组件的扫描链选择逻辑，以及覆盖耦合到扫描链选择逻辑的选择逻辑。扫描链选择逻辑在主计算机的指导下，将各种组件选择为扫描链的成员。覆盖选择逻辑检测扫描链中的变化，从而阻止整个扫描链的进行。

8. 发明授权

US07890316B2 Synchronizing on-chip data processor trace and timing information for export 有权
标题翻译：同步片上数据处理器跟踪和定时信息进行导出
公开(公告)号：US07890316B2
公开(公告)日：2011-02-15
申请号：US11382140
申请日：2006-05-08
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G06F9/455
CPC分类号： G01R31/31705 , G06F9/455 , G06F11/261 , G06F11/3466 , G06F11/3632 , G06F11/3636 , G06F11/364 , G06F11/3648 , G06F11/3656 , Y02D10/34 , Y02T10/82 , Y10S370/914
摘要： Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.
摘要翻译：可以提供指示数据处理器的内部操作的仿真信息供数据处理器外部的装置使用。提供指示由数据处理器执行的数据处理操作的仿真跟踪信息流。还提供了指示数据处理器用于执行数据处理操作的时钟的操作的定时信息流。跟踪流和定时流在其中插入了指示跟踪信息和定时信息之间的时间关系的信息。

9. 发明授权

US06754599B2 Debug output loosely coupled with processor block 有权
标题翻译：调试输出与处理器块松动耦合
公开(公告)号：US06754599B2
公开(公告)日：2004-06-22
申请号：US09740868
申请日：2000-12-21
申请人： Gary L. Swoboda , Robert A. McGowan
发明人： Gary L. Swoboda , Robert A. McGowan
IPC分类号： G01R2500
CPC分类号： G06F11/3636 , G06F11/3656
摘要： An intergrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. Accordingly, the trace export can operate at a frequency independent of the operation circuit.
摘要翻译：构成便于调试和仿真的集成电路包括功能时钟电路和与功能时钟同步工作的操作电路。跟踪触发电路在检测到运算电路内的预定条件时触发跟踪操作。 FIFO缓冲区接收通过跟踪端口导出的跟踪数据。集成电路包括可以与功能时钟或参考时钟同步的振荡器时钟电路。跟踪触发电路和FIFO输入在功能时钟上工作。 FIFO输出和跟踪端口在振荡器时钟上工作。因此，迹线可以全部在功能时钟上运行，或者在功能时钟和参考时钟之间分配。因此，轨迹输出可以以与运行电路无关的频率工作。

10. 发明授权

US08607088B2 Synchronizing remote devices with synchronization sequence on JTAG control lead 有权
标题翻译：在JTAG控制引线上同步具有同步序列的远程设备
公开(公告)号：US08607088B2
公开(公告)日：2013-12-10
申请号：US13226058
申请日：2011-09-06
申请人： Gary L. Swoboda
发明人： Gary L. Swoboda
IPC分类号： G06F1/04
CPC分类号： G01R31/3177 , G01R31/317 , G06F1/12 , G06F1/3206 , G06F11/221 , G06F11/2284 , G06F11/267 , H04L7/046
摘要： A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.
摘要翻译：一种方法包括一种系统，该系统包括耦合到根据主机设备和所有远程设备在系统操作期间跟随的状态图主动操作的第一远程设备的主机设备。该方法还包括在主机设备和第一远程设备根据状态图主动操作时加电第二远程设备。第二个远程设备确定是初始化为标准协议还是高级协议。当确定初始化为高级协议时，第二远程设备然后等待同步点序列。

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