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1. 发明申请

US20060244470A1 Probe card configuration for low mechanical flexural strength electrical routing substrates 失效
公开(公告)号：US20060244470A1
公开(公告)日：2006-11-02
申请号：US11479068
申请日：2006-06-30
申请人： Makarand Shinde , Richard Larder , Timothy Cooper , Ravindra Shenoy , Benjamin Eldridge
发明人： Makarand Shinde , Richard Larder , Timothy Cooper , Ravindra Shenoy , Benjamin Eldridge
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07378
摘要： A mechanical support configuration for a probe card of a wafer test system is provided to increase support for a very low flexural strength substrate that supports spring probes. Increased mechanical support is provided by: (1) a frame around the periphery of the substrate having an increased sized horizontal extension over the surface of the substrate; (2) leaf springs with a bend enabling the leaf springs to extend vertically and engage the inner frame closer to the spring probes; (3) an insulating flexible membrane, or load support member machined into the inner frame, to engage the low flexural strength substrate farther away from its edge; (4) a support structure, such as support pins, added to provide support to counteract probe loading near the center of the space transformer substrate; and/or (5) a highly rigid interface tile provided between the probes and a lower flexural strength space transformer substrate.

2. 发明授权

US06750726B1 Oscillator circuit with flicker noise suppression and method for operating the same 失效
标题翻译：具有闪烁噪声抑制的振荡器电路及其操作方法
公开(公告)号：US06750726B1
公开(公告)日：2004-06-15
申请号：US10301099
申请日：2002-11-20
申请人： Chih-Jen Hung , Ravindra Shenoy , Samuel W. Sheng
发明人： Chih-Jen Hung , Ravindra Shenoy , Samuel W. Sheng
IPC分类号： H03B508
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1221 , H03B5/124 , H03B2202/027
摘要： An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.
摘要翻译：振荡电路包括电负载，第一金属氧化物半导体（MOS）器件，第二MOS器件和负反馈电路。电负载耦合在第一节点和第二节点之间。第一MOS器件耦合在第一节点和第三节点之间，并且控制从第一节点流向第三节点的第一电流。第二MOS器件耦合在第二节点和第四节点之间，并且控制从第二节点流向第四节点的第二电流。正反馈电路与第一和第二MOS器件形成。正反馈电路具有来自第一和第二节点的输入，并输出到第一和第二MOS器件。负反馈电路具有来自第三和第四节点的输入，并且输出到第一和第二MOS器件。

3. 发明授权

US5486282A Electroetching process for seed layer removal in electrochemical fabrication of wafers 失效
标题翻译：晶圆电化学制造中种子层去除的电蚀工艺
公开(公告)号：US5486282A
公开(公告)日：1996-01-23
申请号：US346996
申请日：1994-11-30
申请人： Madhav Datta , Ravindra Shenoy
发明人： Madhav Datta , Ravindra Shenoy
IPC分类号： C25F3/14 , H01L21/60 , C25D5/10 , C25F3/02
CPC分类号： C25F3/14 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14
摘要： A tool and process for electroetching metal films or layers on a substrate employs a linear electrode and a linear jet of electrolyte squirted from the electrode. The electrode is slowly scanned over the film by a drive mechanism. The current is preferably intermittent. In one embodiment a single wafer surface (substrate) is inverted and the jet is scanned underneath. In another embodiment wafers are held vertically on opposite sides of a holder and two linear electrodes, oriented horizontally and on opposite sides of the holder, are scanned vertically upward at a rate such that the metal layers are completely removed in one pass. The process is especially adapted for fabricating C4 solder balls with triple seed layers of Ti-W (titanium-tungsten alloy) on a substrate, phased Cr-Cu consisting of 50% chromium (Cr) and 50% copper (Cu), and substantially pure Cu. Solder alloys are through-mask electrodeposited on the Cu layer. The seed layers conduct the plating current. During etching the seed layers are removed between the solder bumps to isolate them. The phased Cr-Cu and Cu layers are removed by a single electroetching operation in aqueous potassium sulfate and glycerol with cell voltage set to dissolve the phased layer more quickly than the Cu, avoiding excessive solder bump undercutting in the copper layer. The cell voltage may be such that the solder bump is only slightly undercut so as to form a stepped base C4 structure upon reflowing. Ti-W is removed by a chemical process.
摘要翻译：用于在基板上电蚀金属膜或层的工具和方法采用线性电极和从电极喷射的电解质的线性射流。通过驱动机构将电极缓慢扫描在膜上。电流优选是间歇的。在一个实施例中，单个晶片表面（基板）被倒置并且在下面扫描射流。在另一个实施例中，晶片垂直地保持在保持器的相对侧上，并且水平定向并且在保持器的相对侧上的两个线性电极以一定速度被垂直向上扫描，使得金属层在一次通过中完全去除。该方法特别适用于在基体上制造具有Ti-W（钛 - 钨合金）三重种子层的C4焊球，由50％铬（Cr）和50％铜（Cu）组成的相位Cr-Cu，纯铜。焊接合金是电沉积在Cu层上的通孔掩模。种子层进行电镀电流。在蚀刻期间，在焊料凸块之间移除种子层以隔离它们。通过在硫酸钾水溶液和甘油中通过单次电蚀操作除去相位的Cr-Cu和Cu层，其电池电压设置为比Cu更快地溶解相位层，避免了铜层中过多的焊料凹凸。电池电压可以使得焊料凸块仅略微下切，以便在回流时形成阶梯式基底C4结构。 Ti-W通过化学工艺除去。

4. 发明申请

US20060261827A1 Apparatus And Method For Limiting Over Travel In A Probe Card Assembly 有权
标题翻译：在探测卡组件中限制行驶的装置和方法
公开(公告)号：US20060261827A1
公开(公告)日：2006-11-23
申请号：US11461734
申请日：2006-08-01
申请人： Timothy Cooper , Benjamin Eldridge , Carl Reynolds , Ravindra Shenoy
发明人： Timothy Cooper , Benjamin Eldridge , Carl Reynolds , Ravindra Shenoy
IPC分类号： G01R31/02
CPC分类号： G01R31/2887 , G01R3/00 , G01R31/2886
摘要： Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.
摘要翻译：公开了用于测试半导体器件的方法和装置。相对于探针卡组件的探针，超行程停止限制要测试的设备的行程。采用反馈控制技术来控制装置和探针卡组件的相对运动。探针卡组件包括用于吸收相对于探针卡组件的待测试装置的过度行进的柔性基座。

5. 发明授权

US06304150B1 Double-clamped delay stage and voltage controlled oscillator 有权
标题翻译：双钳位延迟级和压控振荡器
公开(公告)号：US06304150B1
公开(公告)日：2001-10-16
申请号：US09354685
申请日：1999-07-15
申请人： Ravindra Shenoy
发明人： Ravindra Shenoy
IPC分类号： H03B524
CPC分类号： H03K3/0231 , H03K5/133 , H03K2005/0013 , H03K2005/00176 , H03K2005/00182
摘要： A delay cell, a method for generating a delay, and a differential ring oscillator are disclosed. The delay cell provides a stable delay with a low voltage power supply, and has a high power supply rejection ratio. The delay cell generally comprises a first and second input receiver on a first and second branch, respectively, to receive an input to control a current on each branch, each branch includes an output node capacitively coupled to a power supply. Each branch may include a current source coupled between the output node and the power supply and/or a lower limit clamp coupled between the output node and the power supply to maintain an output at the output node above a lower limit. The delay cell may also include a first and a second current diverter coupled to the first and second branch for diverting current on the first and second branch away from the first and second input receiver, respectively. An upper limit clamp may be coupled between the power supply and the first and second current diverters to maintain the output below an upper limit. Inputs to the lower and upper limit clamps may be generated relative to the power supply. The delay cell may further include a tail current source coupled between ground and the input receivers and an upper clamp current source coupled between ground and the first and second current diverters.
摘要翻译：公开了一种延迟单元，一种产生延迟的方法和一种差分环形振荡器。延迟单元为低电压电源提供稳定的延迟，并具有高的电源抑制比。延迟单元通常包括分别在第一和第二分支上的第一和第二输入接收器，以接收输入以控制每个分支上的电流，每个分支包括电容耦合到电源的输出节点。每个分支可以包括耦合在输出节点和电源之间的电流源和/或耦合在输出节点和电源之间的下限钳位，以将输出节点处的输出维持在下限以上。延迟单元还可以包括耦合到第一和第二支路的第一和第二电流分流器，用于分别在第一和第二支路上分流远离第一和第二输入接收器的电流。可以在电源和第一和第二电流分流器之间耦合上限钳位以将输出维持在上限以下。可以相对于电源产生对下限和上限钳位的输入。延迟单元还可以包括耦合在地和输入接收器之间的尾电流源以及耦合在地与第一和第二电流分流器之间的上钳位电流源。

6. 发明申请

US20050156611A1 Probe card configuration for low mechanical flexural strength electrical routing substrates 失效
标题翻译：用于低机械抗弯强度电路基板的探针卡配置
公开(公告)号：US20050156611A1
公开(公告)日：2005-07-21
申请号：US10771099
申请日：2004-02-02
申请人： Makarand Shinde , Richard Larder , Timothy Cooper , Ravindra Shenoy , Benjamin Eldridge
发明人： Makarand Shinde , Richard Larder , Timothy Cooper , Ravindra Shenoy , Benjamin Eldridge
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2889 , G01R1/07378
摘要： A mechanical support configuration for a probe card of a wafer test system is provided to increase support for a very low flexural strength substrate that supports spring probes. Increased mechanical support is provided by: (1) a frame around the periphery of the substrate having an increased sized horizontal extension over the surface of the substrate; (2) leaf springs with a bend enabling the leaf springs to extend vertically and engage the inner frame closer to the spring probes; (3) an insulating flexible membrane, or load support member machined into the inner frame, to engage the low flexural strength substrate farther away from its edge; (4) a support structure, such as support pins, added to provide support to counteract probe loading near the center of the space transformer substrate; and/or (5) a highly rigid interface tile provided between the probes and a lower flexural strength space transformer substrate.
摘要翻译：提供了用于晶片测试系统的探针卡的机械支撑结构，以增加对支撑弹簧探针的极低弯曲强度基底的支撑。通过以下方式提供增加的机械支撑：（1）围绕基板的周边的框架，在基板的表面上具有增大尺寸的水平延伸; （2）具有弯曲的板簧，使得板簧能够垂直延伸并使内框架接近弹簧探头; （3）绝缘柔性膜或加工到内框架中的负载支撑构件，使低弯曲强度基板与其边缘更远地接合; （4）加载支撑结构，例如支撑销，以提供支撑以抵消在空间变压器基板的中心附近的探头负载; 和/或（5）设置在所述探针与下弯曲强度空间变换器基板之间的高刚性界面砖。

7. 发明授权

US5939223A Lithium polymer electrolyte battery for sub-ambient temperature applications 失效
标题翻译：用于亚环境温度应用的锂聚合物电解质电池
公开(公告)号：US5939223A
公开(公告)日：1999-08-17
申请号：US879436
申请日：1997-06-20
申请人： John M. Cotte , Madhav Datta , Ravindra Shenoy
发明人： John M. Cotte , Madhav Datta , Ravindra Shenoy
IPC分类号： H01M4/06 , H01M4/50 , H01M4/62 , H01M4/66 , H01M6/12 , H01M6/16 , H01M6/18 , H01M6/22 , H01M6/50
CPC分类号： H01M6/164 , H01M4/622 , H01M4/667 , H01M6/181 , H01M2200/00 , H01M2300/004 , H01M2300/0085 , H01M4/505 , H01M4/668 , H01M6/12
摘要： A primary lithium battery particularly adapted for use in self-contained self-powered devices (SSPD) for mobile communication and computing products, such as radio frequency identification tags, PCMCIA cards, and smart cards. The battery has a flexible and compact design, and utilizes a solid polymer electrolyte membrane that preferably has a polyacrylonitrile matrix. Performance of the electrolyte membrane is optimized by controlling the amount of aprotic organic solvents within the membrane within a prescribed range of ratios. In so doing, the performance characteristics of the battery closely approximate that of conventional liquid electrolytes without the safety hazards associated with the risk of liquid electrolyte leakage, and exhibit enhanced performance at sub-ambient temperatures. A further feature is that the battery's cathode is encapsulated within a polymeric matrix that eliminates the exposure hazard posed by lithium intercalation compounds used within the cathode.
摘要翻译：特别适用于用于移动通信和计算产品（如射频识别标签，PCMCIA卡和智能卡）的自包含自供电设备（SSPD）中的主要锂电池。电池具有灵活且紧凑的设计，并且使用优选具有聚丙烯腈基质的固体聚合物电解质膜。通过在规定的比例范围内控制膜内非质子有机溶剂的量来优化电解质膜的性能。在这样做时，电池的性能特性与常规液体电解质的性能特性密切相关，而没有与液体电解质渗漏的风险相关的安全隐患，并且在低于环境温度下表现出更好的性能。另一个特征是电池的阴极被封装在聚合物基质内，消除了在阴极内使用的锂嵌入化合物引起的暴露危害。

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