专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080205566A1 CLOSED LOOP SUB-CARRIER SYNCHRONIZATION SYSTEM 失效
标题翻译：关闭环路子载波同步系统
公开(公告)号：US20080205566A1
公开(公告)日：2008-08-28
申请号：US12118124
申请日：2008-05-09
申请人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
发明人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
IPC分类号： H04L7/00
CPC分类号： H04N9/78 , H04N9/44
摘要： A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received subcarrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
摘要翻译：一种用于在信号处理系统中同步子载波的系统和方法。本发明的各个方面可以包括接收采样信号的方法步骤和结构。各个方面可以基于采样信号产生同步信号。各方面可以生成并存储所接收的采样信号的裁剪版本。各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。各个方面可以基于同步信号，将恢复的采样信号粗略地与接收的采样信号同步。各个方面可以确定输出恢复采样信号和输出接收副载波之间的相位差。响应于确定的相位差，各个方面可以调整恢复的采样信号的相位。

2. 发明申请

US20060268992A1 Data and phase locking buffer design in a two-way handshake system 有权
公开(公告)号：US20060268992A1
公开(公告)日：2006-11-30
申请号：US11140833
申请日：2005-05-31
申请人： Genkun Yang , Ramkumar Prakasam
发明人： Genkun Yang , Ramkumar Prakasam
IPC分类号： H04N11/04
CPC分类号： G06F9/3869 , H04N19/42 , H04N19/86
摘要： A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.

3. 发明授权

US08861602B2 Motion vector reconstruction in an entropy decoder 有权
标题翻译：熵解码器中的运动矢量重构
公开(公告)号：US08861602B2
公开(公告)日：2014-10-14
申请号：US11154325
申请日：2005-06-16
申请人： Alexander MacInnis , Ramkumar Prakasam , Sheng Zhong
发明人： Alexander MacInnis , Ramkumar Prakasam , Sheng Zhong
IPC分类号： H04N7/12 , H04N5/14
CPC分类号： H04N5/145
摘要： Presented herein are system(s), method(s), and apparatus for motion vector reconstruction in an entropy decoder. In one embodiment of the present invention, there is presented a method for decoding a bitstream. The method comprises reconstructing at least one motion vector from the bitstream at a first stage in a pipeline; and entropy decoding the bitstream with the at least one reconstructed motion vector at the first stage.
摘要翻译：这里呈现的是用于熵解码器中的运动矢量重建的系统，方法和装置。在本发明的一个实施例中，提供了一种用于对比特流进行解码的方法。该方法包括在流水线中的第一级重建来自比特流的至少一个运动矢量; 以及在所述第一阶段利用所述至少一个重构运动矢量熵解码所述比特流。

4. 发明授权

US07529330B2 Closed loop sub-carrier synchronization system 失效
标题翻译：闭环子载波同步系统
公开(公告)号：US07529330B2
公开(公告)日：2009-05-05
申请号：US12118124
申请日：2008-05-09
申请人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
发明人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
IPC分类号： H04L7/00
CPC分类号： H04N9/78 , H04N9/44
摘要： A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
摘要翻译：一种用于在信号处理系统中同步子载波的系统和方法。本发明的各个方面可以包括接收采样信号的方法步骤和结构。各个方面可以基于采样信号产生同步信号。各方面可以生成并存储所接收的采样信号的裁剪版本。各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。各个方面可以基于同步信号，将恢复的采样信号粗略地与接收的采样信号同步。各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。响应于确定的相位差，各个方面可以调整恢复的采样信号的相位。

5. 发明授权

US07372929B2 Closed loop sub-carrier synchronization system 有权
标题翻译：闭环子载波同步系统
公开(公告)号：US07372929B2
公开(公告)日：2008-05-13
申请号：US10794601
申请日：2004-03-05
申请人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
发明人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
IPC分类号： H04L7/00
CPC分类号： H04N9/78 , H04N9/44
摘要： A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
摘要翻译：一种用于在信号处理系统中同步子载波的系统和方法。本发明的各个方面可以包括接收采样信号的方法步骤和结构。各个方面可以基于采样信号产生同步信号。各方面可以生成并存储所接收的采样信号的裁剪版本。各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。各个方面可以基于同步信号，将恢复的采样信号粗略地与接收的采样信号同步。各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。响应于确定的相位差，各个方面可以调整恢复的采样信号的相位。

6. 发明授权

US08130885B2 Closed loop sub-carrier synchronization system 失效
标题翻译：闭环子载波同步系统
公开(公告)号：US08130885B2
公开(公告)日：2012-03-06
申请号：US12433396
申请日：2009-04-30
申请人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
发明人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
IPC分类号： H04L7/00
CPC分类号： H04N9/78 , H04N9/44
摘要： A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
摘要翻译：一种用于在信号处理系统中同步子载波的系统和方法。本发明的各个方面可以包括接收采样信号的方法步骤和结构。各个方面可以基于采样信号产生同步信号。各方面可以生成并存储所接收的采样信号的裁剪版本。各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。各个方面可以基于同步信号，将恢复的采样信号粗略地与接收的采样信号同步。各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。响应于确定的相位差，各个方面可以调整恢复的采样信号的相位。

7. 发明申请

US20090213266A1 CLOSED LOOP SUB-CARRIER SYNCHRONIZATION SYSTEM 失效
标题翻译：关闭环路子载波同步系统
公开(公告)号：US20090213266A1
公开(公告)日：2009-08-27
申请号：US12433396
申请日：2009-04-30
申请人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
发明人： Alexander G. MacInnis , Aleksandr Movshovich , Brad Delanghe , Ramkumar Prakasam
IPC分类号： H04N5/04 , H04L7/00
CPC分类号： H04N9/78 , H04N9/44
摘要： A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
摘要翻译：一种用于在信号处理系统中同步子载波的系统和方法。本发明的各个方面可以包括接收采样信号的方法步骤和结构。各个方面可以基于采样信号产生同步信号。各方面可以生成并存储所接收的采样信号的裁剪版本。各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。各个方面可以基于同步信号，将恢复的采样信号粗略地与接收的采样信号同步。各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。响应于确定的相位差，各个方面可以调整恢复的采样信号的相位。

8. 发明授权

US09182993B2 Data and phase locking buffer design in a two-way handshake system 有权
标题翻译：数据和相位锁定缓冲器设计在双向握手系统中
公开(公告)号：US09182993B2
公开(公告)日：2015-11-10
申请号：US11140833
申请日：2005-05-31
申请人： Genkun Jason Yang , Ramkumar Prakasam
发明人： Genkun Jason Yang , Ramkumar Prakasam
IPC分类号： G06F9/38 , H04N19/42 , H04N19/86
CPC分类号： G06F9/3869 , H04N19/42 , H04N19/86
摘要： A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.
摘要翻译：提供双向握手系统中的数据和相位锁定缓冲器设计，并且可以包括在同步流水线中顺序地锁定数据流水线并排出数据的同步流水线。可以在基本相似的时间通过具有要被接受的数据的相邻流水线阶段同步地接收数据。可以在由同步流水线的当前流水线级生成之后可以处理的就绪信号可以被传送到同步流水线的后续流水线级。可以将接收信号从当前流水线级传送到先前的流水线级。可以产生用于从同步流水线排出数据的漏极信号。可以基于数据中的行信息的结束来断言和解除排除信号。

9. 发明授权

US07769088B2 Context adaptive binary arithmetic code decoding engine 失效
标题翻译：上下文自适应二进制算术码解码引擎
公开(公告)号：US07769088B2
公开(公告)日：2010-08-03
申请号：US10854592
申请日：2004-05-26
申请人： Ramkumar Prakasam , Alexander G MacInnis , Olive Tao , Xiaodong Xie
发明人： Ramkumar Prakasam , Alexander G MacInnis , Olive Tao , Xiaodong Xie
IPC分类号： H04N7/12 , G06K9/46
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： A CABAC decoding engine is devised to cover all aspects of decoding all CABAC-coded syntax elements for AVC. This CABAC decoding engine acts like a Co-processor to another Processor (CPU), which guides the decoding of the bit stream. The CABAC decoding engine or Co-processor has the following highlights: unique context model retrieving and storing method is developed to allow a complete syntax element to be decoded in one hardware (H/W) execution cycle (not necessarily one clock cycle.); H/W assisted approach is provided to accelerate context model initialization; H/W based approach is incorporated to allow fast de-binarization; H/W based approach is provided to allow a block of syntax elements to be decoded instead of one by one; and dedicated H/W accelerators are incorporated to decode special syntax elements.
摘要翻译： CABAC解码引擎被设计为涵盖对AVC的所有CABAC编码语法元素进行解码的所有方面。该CABAC解码引擎像另一个处理器（CPU）的Co处理器一样起作用，它引导了位流的解码。 CABAC解码引擎或协处理器具有以下亮点：开发独特的上下文模型检索和存储方法，以允许在一个硬件（H / W）执行周期（不一定是一个时钟周期）对完整的语法元素进行解码。提供H / W辅助方法来加速上下文模型初始化; 并入基于H / W的方法可实现快速去二值化; 提供基于H / W的方法以允许一个语法元素块被逐个解码; 并集成专用H / W加速器来解码特殊的语法元素。

10. 发明授权

US07630440B2 Context adaptive binary arithmetic code decoding engine 有权
标题翻译：上下文自适应二进制算术码解码引擎
公开(公告)号：US07630440B2
公开(公告)日：2009-12-08
申请号：US10897546
申请日：2004-07-23
申请人： Ramkumar Prakasam
发明人： Ramkumar Prakasam
IPC分类号： H04N7/12 , G06K9/46
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： Methods and systems for selecting contexts during decoding of arithmetic code are disclosed. Aspects of the method may comprise assigning a plurality of default context identifiers to a plurality of current syntax elements within a current macroblock. A plurality of adjacent context identifiers may be acquired, where the adjacent context identifiers may be associated with a plurality of syntax elements within at least one macroblock adjacent to the current macroblock. At least one of the plurality of adjacent context identifiers may be selected utilizing at least one of the default context identifiers. Each of the default context identifiers may comprises a binary value. A top-adjacent context identifier associated with a syntax element within a top-adjacent macroblock to the current macroblock may be acquired. A left-adjacent context identifier associated with a syntax element within a left-adjacent macroblock to the current macroblock may be acquired.
摘要翻译：公开了在算术码解码期间选择上下文的方法和系统。该方法的方面可以包括将多个默认上下文标识符分配给当前宏块内的多个当前语法元素。可以获取多个相邻的上下文标识符，其中相邻的上下文标识符可以与与当前宏块相邻的至少一个宏块内的多个语法元素相关联。可以利用默认上下文标识符中的至少一个来选择多个相邻上下文标识符中的至少一个。每个默认上下文标识符可以包括二进制值。可以获取与当前宏块的顶部相邻宏块内的语法元素相关联的顶部相邻上下文标识符。可以获取与当前宏块的左相邻宏块内的语法元素相关联的左邻近的上下文标识符。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式