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1. 发明授权

US07473953B2 Method for fabricating metallic bit-line contacts 有权
标题翻译：金属位线触点的制造方法
公开(公告)号：US07473953B2
公开(公告)日：2009-01-06
申请号：US11929215
申请日：2007-10-30
申请人： Ralf Staub , Jürgen Amon , Norbert Urbansky
发明人： Ralf Staub , Jürgen Amon , Norbert Urbansky
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76807 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L27/10829 , H01L27/10885 , H01L27/10888 , H01L27/10894 , Y10S257/905
摘要： A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
摘要翻译：提供了一种存储单元及其形成方法。为了在半导体晶片上的动态存储单元的位线和选择晶体管之间进行接触，接触孔填充有金属或金属合金。可以在半导体衬底和金属填充物之间引入衬里层。半导体衬底在接触孔中具有掺杂区域。

2. 发明授权

US07265405B2 Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts 有权
标题翻译：用于制造用于集成电路的触点的方法，以及具有这种触点的半导体部件
公开(公告)号：US07265405B2
公开(公告)日：2007-09-04
申请号：US10754439
申请日：2004-01-09
申请人： Kae-Horng Wang , Ralf Staub , Matthias Krönke
发明人： Kae-Horng Wang , Ralf Staub , Matthias Krönke
IPC分类号： H01L29/94
CPC分类号： H01L27/10888 , H01L21/76895 , H01L21/76897 , H01L27/10829
摘要： One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.
摘要翻译：在半导体晶片的一个或多个有源区上产生一个（或多个）触点，一个或多个隔离的控制线可以布置在与其进行接触的有源区上。控制线可以例如是栅极线。以下列方式制造半导体部件：向半导体晶片施加多晶硅层，构图多晶硅层，以在有源区上方产生多晶硅接触，多晶硅接触至少部分覆盖两个控制线，将第一绝缘体层施加到半导体晶片，其中嵌入多晶硅接触部分地去除第一绝缘体层，使得至少多晶硅接触的上表面未被覆盖，以及向半导体晶片施加金属层以便与多晶硅接触进行电接触。

3. 发明授权

US07084027B2 Method for producing an integrated circuit 失效
标题翻译：集成电路的制造方法
公开(公告)号：US07084027B2
公开(公告)日：2006-08-01
申请号：US10399985
申请日：2001-09-18
申请人： Andreas Hilliger , Ralf Staub , Eike Lüken
发明人： Andreas Hilliger , Ralf Staub , Eike Lüken
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/76897
摘要： The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substrate (1) with a contacting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate (1): providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area (10′) in at least the area above the contact hole (KL); providing at least three trenches (BG1; BG2; BG3), the first (BG1) of which is arranged next to the contact hole (KL), a second (BG2) is disposed across the contact hole (KL) and a third (BG3) is next to the contact hole (KL). The spacer area (10′) is placed between the first and the second trench (BG1; BG2) and the second and the third trench (BG2; BG3); filling the trenches (BG1; BG2; BG3) with a conductive material; and chemical-mechanical polishing of conductive material for producing three separated trenches (BL1; BL2; BL3).
摘要翻译：本发明涉及一种用于制造集成电路的方法，包括以下步骤：制备具有接触电路区域（SS）的半导体衬底（1）; 在所述半导体基板（1）的表面上提供绝缘层（IS）：在所述绝缘层（IS）中提供与所述电路区域（SS）接触的接触孔（KL）; 在至少所述接触孔（KL）上方的区域中提供绝缘间隔区域（10'）; 提供至少三个沟槽（BG1; BG2; BG3），其第一（BG1）布置在接触孔（KL）旁边，第二（BG 2）跨越接触孔（KL）设置，并且第三（BG 3）在接触孔（KL）旁边。间隔区域（10'）位于第一和第二沟槽（BG1; BG2）和第二和第三沟槽（BG2; BG3）之间; 用导电材料填充沟槽（BG1; BG2; BG3）; 和用于制造三个分离的沟槽（BL 1; BL 2; BL 3）的导电材料的化学机械抛光。

4. 发明申请

US20080048229A1 METHOD FOR FABRICATING METALLIC BIT-LINE CONTACTS 有权
标题翻译：制造金属线对联系的方法
公开(公告)号：US20080048229A1
公开(公告)日：2008-02-28
申请号：US11929215
申请日：2007-10-30
申请人： Ralf Staub , Jurgen Amon , Norbert Urbansky
发明人： Ralf Staub , Jurgen Amon , Norbert Urbansky
IPC分类号： H01L27/108
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76807 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L27/10829 , H01L27/10885 , H01L27/10888 , H01L27/10894 , Y10S257/905
摘要： A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
摘要翻译：提供了一种存储单元及其形成方法。为了在半导体晶片上的动态存储单元的位线和选择晶体管之间进行接触，接触孔填充有金属或金属合金。可以在半导体衬底和金属填充物之间引入衬里层。半导体衬底在接触孔中具有掺杂区域。

5. 发明授权

US07326985B2 Method for fabricating metallic bit-line contacts 失效
标题翻译：金属位线触点的制造方法
公开(公告)号：US07326985B2
公开(公告)日：2008-02-05
申请号：US10692024
申请日：2003-10-23
申请人： Ralf Staub , Jürgen Amon , Norbert Urbansky
发明人： Ralf Staub , Jürgen Amon , Norbert Urbansky
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76807 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L27/10829 , H01L27/10885 , H01L27/10888 , H01L27/10894 , Y10S257/905
摘要： A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
摘要翻译：提供了一种存储单元及其形成方法。为了在半导体晶片上的动态存储单元的位线和选择晶体管之间进行接触，接触孔填充有金属或金属合金。可以在半导体衬底和金属填充物之间引入衬里层。半导体衬底在接触孔中具有掺杂区域。

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