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1. 发明授权

US06716650B2 Interface void monitoring in a damascene process 失效
标题翻译：界面在大马士革过程中进行监视
公开(公告)号：US06716650B2
公开(公告)日：2004-04-06
申请号：US10121122
申请日：2002-04-11
申请人： Eckhard Langer , Frank Koschinsky , Volker Kahlert , Peter Hübler
发明人： Eckhard Langer , Frank Koschinsky , Volker Kahlert , Peter Hübler
IPC分类号： H01L2166
CPC分类号： H01L21/76849 , H01L21/76877
摘要： For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.
摘要翻译：为了确定集成电路中的互连的质量，特别是在镶嵌应用中，公开了一种监测空隙的方法，其中阻挡金属层直接沉积在平坦化金属上以提供不需要被破坏的大面积表面进一步分析金属与阻挡金属层之间的界面。可以通过使用以背散射模式操作的电子显微镜来进行分析。

2. 发明授权

US06613660B2 Metallization process sequence for a barrier metal layer 有权
标题翻译：阻挡金属层的金属化工艺顺序
公开(公告)号：US06613660B2
公开(公告)日：2003-09-02
申请号：US10131699
申请日：2002-04-24
申请人： Volker Kahlert , Frank Koschinsky , Peter Hübler
发明人： Volker Kahlert , Frank Koschinsky , Peter Hübler
IPC分类号： H01L2144
CPC分类号： H01L21/76843
摘要： In an in situ damascene metallization process employing a barrier layer between the metal and the dielectric, the generation of voids, especially at the bottom of vias, can be significantly reduced or even completely avoided by maintaining the surface temperature below a critical temperature during deposition of the barrier material.
摘要翻译：在使用金属和电介质之间的阻挡层的原位金刚石金属化工艺中，特别是在通孔底部的空隙的产生可以通过在沉积期间将表面温度保持在临界温度以下来显着降低甚至完全避免阻隔材料。

3. 发明授权

US06806191B2 Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same 失效
标题翻译：具有增加的电迁移阻力的铜线的半导体器件及其形成方法
公开(公告)号：US06806191B2
公开(公告)日：2004-10-19
申请号：US10304579
申请日：2002-11-26
申请人： Christian Zistl , Jörg Hohage , Hartmut Rülke , Peter Hübler
发明人： Christian Zistl , Jörg Hohage , Hartmut Rülke , Peter Hübler
IPC分类号： H01L2144
CPC分类号： H01L21/76886 , H01L21/02074 , H01L21/32136 , H01L21/76849 , H01L21/76867
摘要： A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.
摘要翻译：在图案化电介质层中形成的铜线具有在其表面上形成的铜/硅膜，以基本上抑制通过该表面的电迁移路径。在原位处理中，暴露的铜表面首先通过包括氮和氨的反应性等离子体环境进行清洁，并且在一定的清洁时间之后，将包含硅的气态化合物（例如硅烷）添加到反应性等离子体环境中以形成铜 /硅膜。另外，可以沉积覆盖层，其中由于铜/硅膜，可以使用任何沉积技术或甚至旋涂。

4. 发明授权

US06964874B2 Void formation monitoring in a damascene process 失效
标题翻译：大马士革过程中的空洞形成监测
公开(公告)号：US06964874B2
公开(公告)日：2005-11-15
申请号：US10259037
申请日：2002-09-27
申请人： Thomas Werner , Peter Hübler , Frank Koschinsky
发明人： Thomas Werner , Peter Hübler , Frank Koschinsky
IPC分类号： H01L21/288 , H01L21/768 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L21/2885 , H01L21/76807 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.
摘要翻译：本发明提供了一种在大马士革互连过程中监测空隙形成的技术。根据本发明，提供一种测试结构，其包括具有至少一个不同横截面几何参数的至少两个镶嵌结构。为了监测空隙形成，切割测试结构以露出镶嵌结构的横截面视图。然后检查横截面图，并在每个镶嵌结构中研究空隙形成。本发明特别适用于多级铜基双镶嵌互连工艺，以监测阻挡层和底部金属沟槽之间界面处的空隙。本发明允许通过仅在芯片上定位一个结构并且仅执行一个切割来监视空隙形成。

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