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    • 3. 发明申请
    • Method and apparatus for encoding symbols carrying payload data for watermarking an audio or video signal, and method and apparatus for decoding symbols carrying payload data of a watermarked audio or video signal
    • 用于编码携带用于对音频或视频信号进行加水印的有效载荷数据的符号的符号的方法和装置,以及用于解码承载带有水印的音频或视频信号的有效载荷数据的符号的方法和装置
    • US20060212710A1
    • 2006-09-21
    • US11376530
    • 2006-03-15
    • Peter BaumWalter Voessing
    • Peter BaumWalter Voessing
    • H04L9/00
    • G06T1/005G06T1/0028G06T2201/0065G06T2201/0202
    • Watermark information (denoted WM) consists of several symbols which are embedded continuously in an audio or a video signal. At decoder site the WM is regained using correlation of the received signal with an m-sequence if Spread Spectrum is used. In some watermark technology the watermark information is transmitted asynchronously, i.e. it is continuously tested whether or not WM can be embedded imperceptible within the audio or video signals. Only if this is true a WM frame is transmitted. But a WM frame consists of some tens of symbols, each carrying one or more bits which are transmitted synchronously. That means, if the period in which the WM can be embedded is shorter than the frame length, some symbols cannot be recovered at receiver side. According to the invention, each WM symbol carries an ID item in addition to its normal payload, and it is already tested in the encoder whether or not the signal is good enough so that the embedded symbol can be recovered at decoder side. If true, it is embedded. If not true, no WM is embedded for the length of one symbol and the test is repeated for the following symbol. The sequence of IDs is known at the encoder which can therefore detect using the ID whether or not a symbol has been skipped.
    • 水印信息(表示为WM)由连续嵌入音频或视频信号的几个符号组成。 在解码器位置,如果使用扩频,则使用接收信号与m序列的相关性来重新获得WM。 在一些水印技术中,水印信息是异步发送的,即连续测试WM是否可以在音频或视频信号内嵌入不可察觉的信号。 只有这样,才发送WM帧。 但是WM帧由几十个符号组成,每个符号携带一个或多个同步传输的位。 这意味着,如果可嵌入WM的周期短于帧长度,则在接收机侧无法恢复某些符号。 根据本发明,每个WM符号除了其正常有效载荷之外还携带ID项目,并且已经在编码器中测试了信号是否足够好,使得嵌入符号可以在解码器侧被恢复。 如果是,它是嵌入的。 如果不是真的,则不会为一个符号的长度嵌入WM,并为以下符号重复测试。 ID的序列在编码器处是已知的,因此可以使用ID来检测符号是否被跳过。
    • 6. 发明申请
    • Method and apparatus for transmitting watermark data bits using a spread spectrum, and for regaining watermark data bits embedded in a spread spectrum
    • 用于使用扩展频谱发送水印数据位的方法和装置,以及用于恢复嵌入在扩展频谱中的水印数据位
    • US20070136595A1
    • 2007-06-14
    • US10581771
    • 2004-09-13
    • Peter BaumWalter Voessing
    • Peter BaumWalter Voessing
    • H04L9/00
    • H04H20/31G10L19/018G11B20/00891H04H2201/50
    • Spread spectrum technology and the related inserted or added information signal can be used for implementing watermarking digital audio signals. A known processing for retrieving at receiver or decoder side the watermark signal information bit from the spread spectrum is convolving the received or replayed spectrum with a spreading function that is time-inverse with respect to the original spreading function. If BPSK modulation was used for applying the spread spectrum function, the output is a peak at the middle of the sequence of correlation values, the sign of such peak representing the value of the desired watermark signal information bit. According to the invention, in order to cope with echo distortions, two or more orthogonal spreading sequences are used at encoder side with the original or encoded audio signal in baseband. When applying the corresponding time-inverse orthogonal spreading sequences at decoder side, echoes that are longer than each one of spreading sequence's lengths can be fully removed. The spreading sequences applied can be modified at decoder side according to estimated echo delay values.
    • 扩展频谱技术和相关的插入或添加信息信号可用于实现水印数字音频信号。 在接收机或解码​​器侧检索来自扩频的水印信号信息比特的已知处理是用接收或重放的频谱与相对于原始扩展函数的时间反相的扩展函数进行卷积。 如果使用BPSK调制来应用扩频函数,则输出是相关值序列中间的峰值,这种峰值的符号表示所需水印信号信息位的值。 根据本发明,为了应对回波失真,在编码器侧使用原始或编码的音频信号在基带中的两个或更多个正交扩频序列。 当在解码器侧应用相应的时间 - 逆正交扩频序列时,可以完全去除比扩展序列长度中的每一个更长的回波。 可以根据估计的回波延迟值在解码器侧修改所应用的扩展序列。
    • 9. 发明授权
    • Automobile drum brake
    • 汽车鼓式制动器
    • US4730707A
    • 1988-03-15
    • US943221
    • 1986-12-18
    • David J. EdwardsPeter Baum
    • David J. EdwardsPeter Baum
    • F16D51/18F16D65/09F16D65/14F16D51/24
    • F16D51/18F16D65/09F16D2125/66
    • For automobile drum brakes of the simplex and duo-duplex forms of construction, each having two brake shoes (10) floatingly mounted on a brake bracket (1), a special support is proposed for the one end of the brake shoe web (10) of each brake shoe (8), this support being constituted basically of a support pin (26) rotatable about its central axis, which possesses a recessed bearing surface, on which a corresponding counter-surface (35) of the brake shoe web (10) is slidably journalled. The new support makes possible the maintaining of a constant brake coefficient throughout the full range of wear of the brake lining (12).
    • 对于具有浮动地安装在制动支架(1)上的两个制动蹄(10)的单面和双面双面结构形式的汽车鼓式制动器,提出了用于制动蹄片(10)一端的专用支架, 每个制动蹄(8)上的该支撑件基本上由能够围绕其中心轴线旋转的支撑销(26)构成,该支承销具有凹入的支承表面,煞车靴腹板(10)的对应的对置表面(35) )可滑动轴承。 新的支撑件使得可以在制动衬片(12)的整个磨损范围内保持恒定的制动系数。
    • 10. 发明授权
    • Banked memory circuit
    • 存储器电路
    • US4601018A
    • 1986-07-15
    • US696038
    • 1985-01-29
    • Allen BaumPeter Baum
    • Allen BaumPeter Baum
    • G06F12/06G06T1/60G11C8/12G11C11/406G11C11/30
    • G06F12/0623G06T1/60G11C11/406G11C8/12
    • A memory circuit for interconnection to a computer including several memory banks, each bank including memory for the storage of information for the total address space addressable by the data processor. The memory circuit further includes a bank selection circuit connected to the data processor for receiving data representing a selected one of the memory banks. The memory circuit further includes a memory access circuit that determines from the bank selection circuit which one of the memory banks has been selected and provides alternating access between the selected memory bank and a specific memory bank in accordance with a timing signal from the data processor. The specific data bank includes display information and is accessed by the data processor during each interval when information is being output to the display. The memory circuit further includes a memory refresh circuit to refresh the memory banks by refreshing a limited number of memory banks during successive refresh time intervals in accordance with control signals from the display circuitry.
    • 一种用于与包括几个存储体的计算机互连的存储器电路,每个存储体包括用于存储由数据处理器寻址的总地址空间的信息的存储器。 存储器电路还包括连接到数据处理器的存储体选择电路,用于接收表示所选存储体组中的一个的数据。 存储器电路还包括存储器存取电路,其从存储体选择电路确定已经选择了哪个存储体,并且根据来自数据处理器的定时信号,提供所选存储体和特定存储体之间的交替存取。 特定数据库包括显示信息,并且当信息被输出到显示器时在数据处理器在每个间隔期间被访问。 存储器电路还包括存储器刷新电路,以根据来自显示电路的控制信号在连续的刷新时间间隔期间刷新有限数量的存储体来刷新存储体。