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1. 发明授权

US07282937B2 On-chip frequency degradation compensation 有权
公开(公告)号：US07282937B2
公开(公告)日：2007-10-16
申请号：US10751132
申请日：2003-12-31
申请人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

2. 发明申请

US20050140418A1 On-chip frequency degradation compensation 有权
标题翻译：片上频率降级补偿
公开(公告)号：US20050140418A1
公开(公告)日：2005-06-30
申请号：US10751132
申请日：2003-12-31
申请人： Ravisangar Muniandy , Gregory Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory Taylor , Payman Aminzadeh
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
摘要翻译：本发明的实施例包括三个可靠性振荡器。在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

3. 发明授权

US07501845B2 On-chip frequency degradation compensation 失效
标题翻译：片上频率降级补偿
公开(公告)号：US07501845B2
公开(公告)日：2009-03-10
申请号：US12082065
申请日：2008-04-07
申请人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
摘要翻译：本发明的实施例包括三个可靠性振荡器。在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

4. 发明申请

US20080252329A1 On-chip frequency degradation compensation 失效
公开(公告)号：US20080252329A1
公开(公告)日：2008-10-16
申请号：US12082065
申请日：2008-04-07
申请人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

5. 发明授权

US07394274B2 On-chip frequency degradation compensation 有权
标题翻译：片上频率降级补偿
公开(公告)号：US07394274B2
公开(公告)日：2008-07-01
申请号：US11879645
申请日：2007-07-17
申请人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory F. Taylor , Payman Aminzadeh
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
摘要翻译：本发明的实施例包括三个可靠性振荡器。在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

6. 发明申请

US20070257697A1 On-chip frequency degradation compensation 有权
标题翻译：片上频率降级补偿
公开(公告)号：US20070257697A1
公开(公告)日：2007-11-08
申请号：US11879645
申请日：2007-07-17
申请人： Ravisangar Muniandy , Gregory Taylor , Payman Aminzadeh
发明人： Ravisangar Muniandy , Gregory Taylor , Payman Aminzadeh
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
摘要翻译：本发明的实施例包括三个可靠性振荡器。在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

7. 发明授权

US06707120B1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06707120B1
公开(公告)日：2004-03-16
申请号：US09097991
申请日：1998-06-16
申请人： Payman Aminzadeh , Reza Arghavani , Peter Moon
发明人： Payman Aminzadeh , Reza Arghavani , Peter Moon
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/3144 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
摘要翻译：公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。在栅电极上生长氧化物。该氧化物通过氮化和退火得到加强。在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

8. 发明授权

US5827769A Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode 失效
标题翻译：通过对栅电极的侧壁氧化物进行氮化和退火来制造具有增加的热载流子电阻的晶体管的方法
公开(公告)号：US5827769A
公开(公告)日：1998-10-27
申请号：US754219
申请日：1996-11-20
申请人： Payman Aminzadeh , Reza Arghavani , Peter Moon
发明人： Payman Aminzadeh , Reza Arghavani , Peter Moon
IPC分类号： H01L21/314 , H01L21/336 , H01L29/49 , H01L21/31
CPC分类号： H01L29/6659 , H01L21/3144 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
摘要翻译：公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。在栅电极上生长氧化物。该氧化物通过氮化和退火得到加强。在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

9. 发明授权

US5844300A Single poly devices for monitoring the level and polarity of process induced charging in a MOS process 失效
标题翻译：用于监测MOS工艺中过程感应充电的电平和极性的单个多晶硅器件
公开(公告)号：US5844300A
公开(公告)日：1998-12-01
申请号：US716843
申请日：1996-09-19
申请人： Mohsen Alavi , Payman Aminzadeh , Robert A. Gasser , Sunit Tyagi , Gilroy J. Vandentop
发明人： Mohsen Alavi , Payman Aminzadeh , Robert A. Gasser , Sunit Tyagi , Gilroy J. Vandentop
IPC分类号： H01L27/115 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L27/115
摘要： A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.
摘要翻译：一种使用形成浮栅的单层多晶硅监测过程感应电荷的监测装置。该器件包括两个电容器，一个用于充电，另一个用于放电n沟道晶体管的浮置栅极。描述允许监测正电荷，负电荷以及正电荷和负电荷两者的实施例。与用于线路末端监测的一些现有技术设备相反，该设备可重复使用并且适合于在线监测。

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