专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5584017A Cache control which inhibits snoop cycles if processor accessing memory is the only processor allowed to cache the memory location 失效
标题翻译：如果处理器访问存储器是允许缓存内存位置的唯一处理器，则禁止侦听周期的缓存控制
公开(公告)号：US5584017A
公开(公告)日：1996-12-10
申请号：US425351
申请日：1995-04-18
申请人： Paul R. Pierce , Anthony M. Zilka
发明人： Paul R. Pierce , Anthony M. Zilka
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0831
摘要： A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.
摘要翻译：一种多处理器高速缓存控制系统，其中高速缓存控制信息被编码到存储器访问请求的地址位中。编码高速缓存控制信息用于优化缓存控制功能。每个存储器访问请求由至少两个元素组成。首先，提供地址字段以定义所需数据项的位置。其次，在每个存储器访问请求中的高速缓存控制字段中提供高速缓存控制信息。高速缓存控制字段包括定义地址字段和与多处理器系统中的处理器相关联的多个本地高速缓存之间的关系的多个位。该关系确定多个本地高速缓存中的哪一个可以缓存由地址字段内的地址引用的数据项。

2. 发明授权

US5511226A System for generating snoop addresses and conditionally generating source addresses whenever there is no snoop hit, the source addresses lagging behind the corresponding snoop addresses 失效
标题翻译：用于生成窥探地址的系统，并且每当没有窥探命中时有条件地生成源地址，源地址落后于相应的侦听地址
公开(公告)号：US5511226A
公开(公告)日：1996-04-23
申请号：US935035
申请日：1992-08-25
申请人： Anthony M. Zilka
发明人： Anthony M. Zilka
IPC分类号： G06F12/08 , G06F12/00 , G06F12/06 , G06F12/10
CPC分类号： G06F12/0835
摘要： A processor and a memory address bus, a processor and a memory data bus, and a data transfer control unit are provided to a multiprocessor computer system comprising a first and a second processor, a first and a second corresponding private cache, a pipelined memory shared among the processors, an I/O device, and a cache coherency mechanism for maintaining cache coherency. I/O data stored in the shared memory are cacheable in the private caches. The processor and memory address and data buses are advantageously used to couple these elements and to control data transfers in and out of the shared memory. All data transfers in and out of the shared memory are made in multiples of the basis on which cache coherency is maintained, and through the data transfer control unit. As a result, minimum complimentary cache coherency actions, in addition to those provided by the cache coherency mechanism, are required of the data transfer control unit and the caches, to allow data to be transferred between the shared memory and the I/O device. Furthermore, successive cache coherency basis transfers between the shared memory and the I/O device are overlapped, thereby improving the overall performance of the multiprocessor computer system.
摘要翻译：处理器和存储器地址总线，处理器和存储器数据总线以及数据传输控制单元被提供到多处理器计算机系统，该多处理器计算机系统包括第一和第二处理器，第一和第二对应的专用高速缓存，流水线存储器共享在处理器中，I / O设备和用于维持高速缓存一致性的高速缓存一致性机制。存储在共享存储器中的I / O数据可以缓存在专用高速缓存中。处理器和存储器地址和数据总线有利地用于耦合这些元件并且控制进出共享存储器的数据传输。进出共享存储器的所有数据传输都是保持高速缓存一致性的基础的倍数，并通过数据传输控制单元进行。因此，需要数据传输控制单元和高速缓存之间的最小补充高速缓存一致性动作以及数据传输控制单元和高速缓存，以便在共享存储器和I / O设备之间传送数据。此外，在共享存储器和I / O设备之间的连续高速缓存一致性传输是重叠的，从而提高了多处理器计算机系统的整体性能。

3. 发明授权

US5526497A System having switch that provides capacitive load isolation 失效
标题翻译：具有提供容性负载隔离的开关的系统
公开(公告)号：US5526497A
公开(公告)日：1996-06-11
申请号：US388583
申请日：1995-02-09
申请人： Anthony M. Zilka , Massoud Taraghi , Paul E. Prince
发明人： Anthony M. Zilka , Massoud Taraghi , Paul E. Prince
IPC分类号： G06F13/40 , G06F13/00 , H03H7/48
CPC分类号： G06F13/4022
摘要： Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.
摘要翻译：使用数据路径专用集成电路（ASIC）交叉开关来耦合计算机系统的组件。多个多位双向寄存器端口使用多位多路复用器电路相互配合。提供给多路复用器的端口选择控制信号通过数据通道ASIC引导数据流。数据通路ASIC将计算机系统的组件电隔离，从而最小化信号线路上的容性负载，并允许信号以高速率传输。数据路径ASIC的控制由外部电路提供，通过消除对任何特定通信协议的依赖来增加交叉开关的灵活性。可以并行地组合多个数据路径ASIC以通过使用位片方案来增加数据流的带宽。

4. 发明授权

US5418911A Data path switch method and apparatus that provides capacitive load isolation 失效
标题翻译：提供容性负载隔离的数据路径切换方法和装置
公开(公告)号：US5418911A
公开(公告)日：1995-05-23
申请号：US896048
申请日：1992-06-09
申请人： Anthony M. Zilka , Massoud Taraghi , Paul E. Prince
发明人： Anthony M. Zilka , Massoud Taraghi , Paul E. Prince
IPC分类号： G06F13/40 , G06F13/00 , H03H7/48
CPC分类号： G06F13/4022
摘要： Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.
摘要翻译：使用数据路径专用集成电路（ASIC）交叉开关来耦合计算机系统的组件。多个多位双向寄存器端口使用多位多路复用器电路相互配合。提供给多路复用器的端口选择控制信号通过数据通道ASIC引导数据流。数据通路ASIC将计算机系统的组件电隔离，从而最小化信号线路上的容性负载，并允许信号以高速率传输。数据路径ASIC的控制由外部电路提供，通过消除对任何特定通信协议的依赖来增加交叉开关的灵活性。可以并行地组合多个数据路径ASIC以通过使用位片方案来增加数据流的带宽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式