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1. 发明授权

US6069496A CMOS circuit technique for improved switching speed of single-ended and differential dynamic logic 有权
标题翻译： CMOS电路技术，提高单端和差分动态逻辑的开关速度
公开(公告)号：US6069496A
公开(公告)日：2000-05-30
申请号：US207303
申请日：1998-12-08
申请人： Paul L. Perez
发明人： Paul L. Perez
IPC分类号： H03K19/017 , H03K19/096
CPC分类号： H03K19/01728
摘要： A method and apparatus for improving the forward path switching speed of a complementary CMOS inverter is presented. A large P-type to N-type FET ratio is used to tune the inverter trigger point to the falling edge of the input signal to the inverter. The high P-type to N-type ratio is made feasible by adding a precharge assist pull-down transistor in parallel on the output node of the inverter.
摘要翻译：提出了一种用于提高互补CMOS反相器的正向路径切换速度的方法和装置。使用大型P型至N型FET比率将逆变器触发点调节到输入信号的下降沿到逆变器。通过在逆变器的输出节点上并联预充电辅助下拉晶体管，可以实现高P型到N型比。

2. 发明申请

US20090031547A1 METHOD OF MANUFACTURING A COMPUTING APPARATUS 审中-公开
标题翻译：制造计算机的方法
公开(公告)号：US20090031547A1
公开(公告)日：2009-02-05
申请号：US11831153
申请日：2007-07-31
申请人： Christian L. Belady , Paul L. Perez
发明人： Christian L. Belady , Paul L. Perez
IPC分类号： B23P11/00 , B25B27/14
CPC分类号： G06F1/181 , G06F1/16 , G06Q10/06 , Y10T29/49831 , Y10T29/53961
摘要： A method of manufacturing a computing apparatus may include providing a plurality of computer components for the computing apparatus. The computing apparatus and the plurality of computer components can be transported from an origin to a geographically distant destination with a transport vehicle. Manufacture of the computing apparatus is substantially completed during the transporting of the computing apparatus.
摘要翻译：计算装置的制造方法可以包括为计算装置提供多个计算机部件。计算装置和多个计算机部件可以使用运输工具从原产地运输到地理上远的目的地。在计算设备的运输期间，计算设备的制造基本完成。

3. 发明授权

US5867644A System and method for on-chip debug support and performance monitoring in a microprocessor 失效
标题翻译：用于微处理器中片上调试支持和性能监控的系统和方法
公开(公告)号：US5867644A
公开(公告)日：1999-02-02
申请号：US711491
申请日：1996-09-10
申请人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
发明人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
IPC分类号： G06F11/36 , G06F11/00
CPC分类号： G06F11/3648 , G06F11/364
摘要： User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.
摘要翻译：用户可配置的诊断硬件包含微处理器，用于调试和监视微处理器的性能。使用方法可编程状态机耦合到片上和片外输入源。状态机可以被编程为寻找由输入源呈现的信号模式，并且通过将某些控制信息驱动到状态机输出总线上来响应定义的模式（或定义的模式的序列）的出现。耦合到输出总线的片上设备采用由总线指示的用户可定义的动作。输入源包括位于微处理器的功能块内的用户可配置比较器。比较器耦合到微处理器内的存储元件，并且被配置为监视节点以确定节点的状态是否与包含在存储元件中的数据匹配。通过改变存储元件中的数据，程序员可以改变比较节点状态的信息，以及进行比较的方法。输出设备包括计数器。计数器输出可以用作状态机输入，因此可以将一个事件定义为发生一定次数的不同事件的功能。输出设备还包括用于产生内部和外部触发的电路。用户可配置的多路复用器电路可以用于将用户可选择的信号从微处理器传送到芯片的输出焊盘，并且选择要用作状态机输入的各种内部信号。

4. 发明授权

US5726596A High-performance, low-skew clocking scheme for single-phase, high-frequency global VLSI processor 失效
标题翻译：用于单相，高频全球VLSI处理器的高性能，低偏移时钟方案
公开(公告)号：US5726596A
公开(公告)日：1998-03-10
申请号：US609592
申请日：1996-03-01
申请人： Paul L. Perez
发明人： Paul L. Perez
IPC分类号： G06F1/10 , H03K5/151 , H03K5/13
CPC分类号： H03K5/1515 , G06F1/10
摘要： A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer for receiving an external global clock and producing a first level global clock. A plurality of second level clock buffers, one corresponding to each localized logic block, receive the first level global clock via protected equal length lines, and each produce a respective second level global clock. Each of the localized logic blocks include a plurality of third level clock buffers, wherein each third level clock buffer receives the second level global clock of its respective localized logic block, and each produces a third level local clock. The third level local clock buffers within each localized logic block generate different clocking schemes from each of the other third level local clock buffers contained within the same localized block. The present invention provides improved performance of global transfers of data between localized logic blocks located on far ends of the chip because the falling edges of the third level overlapping and non-overlapping clock signals CK1, CK1N and CK2, CK2N are coincident to each other.
摘要翻译：提出了一种在具有在其上实现的多个局部逻辑块的VLSI芯片中使用的单相时钟方案。本发明包括用于接收外部全局时钟并产生第一级全局时钟的第一级全局时钟缓冲器。多个第二级时钟缓冲器，一个对应于每个局部逻辑块的第二级时钟缓冲器经受保护的等长线接收第一级全局时钟，并且每个产生相应的第二级全局时钟。每个局部逻辑块包括多个第三电平时钟缓冲器，其中每个第三电平时钟缓冲器接收其各自的局部逻辑块的第二电平全局时钟，并且每个产生第三电平本地时钟。每个局部逻辑块内的第三级本地时钟缓冲器从同一局部块内包含的其他第三级本地时钟缓冲区中的每一个生成不同的时钟方案。本发明提供了由于第三级重叠和不重叠的时钟信号CK1，CK1N和CK2，CK2N的下降沿彼此重合而在位于芯片远端的局部逻辑块之间进行全局数据传输的性能提高。

5. 发明授权

US6003107A Circuitry for providing external access to signals that are internal to an integrated circuit chip package 失效
标题翻译：用于提供对集成电路芯片封装内部信号的外部访问的电路
公开(公告)号：US6003107A
公开(公告)日：1999-12-14
申请号：US707936
申请日：1996-09-10
申请人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Patrick Knebel , Paul L. Perez
发明人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Patrick Knebel , Paul L. Perez
IPC分类号： G06F7/02 , G06F13/00 , G06F7/38 , H01L25/00
CPC分类号： G06F7/02
摘要： Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.
摘要翻译：用于提供对集成电路芯片封装内部信号的外部访问的电路。多个N：1复用器物理地分布在整个集成电路管芯中。每个复用器具有其N个输入耦合到集成电路内的附近的一组N个节点，并且每个多路复用器耦合到可选择信息的源，用于从用于外部访问的N个节点的集合中选择一个节点。每个多路复用器的输出耦合到外部可访问的芯片焊盘。集成电路是微处理器，选择信息的源可以包括存储元件。如果是这样，则提供附加电路用于使用一个或多个微处理器指令将数据从微处理器的寄存器写入存储元件。每个复用器可以耦合到不同的选择信息源，或者所有复用器可以耦合到相同的选择信息。此外，可以提供固定的一组互连轨迹以将固定的一组节点耦合到另外一组外部可访问的芯片焊盘。还可以提供一个或多个M：1多路复用器，其M个输入端耦合到N：1多路复用器的M个不同输出。 M：1多路复用器中的每一个可以耦合到第二选择信息源。优选地，M：1多路复用器的输出将耦合到用于促进集成电路的调试和性能监视的电路。

6. 发明授权

US5886540A Evaluation phase expansion for dynamic logic circuits 失效
标题翻译：动态逻辑电路的评估阶段扩展
公开(公告)号：US5886540A
公开(公告)日：1999-03-23
申请号：US658920
申请日：1996-05-31
申请人： Paul L. Perez
发明人： Paul L. Perez
IPC分类号： H03K19/017 , H03K19/096 , H03K19/00
CPC分类号： H03K19/01728
摘要： An evaluation phase expansion system for increasing the operating frequency of a dynamic logic circuit which includes a plurality of logic stages. The plurality of logic stages are partitioned into a first set of logic stages which are responsive to an early clock signal and which evaluate in an early evaluate phase and a second set of logic stages which are responsive to a late clock signal and which evaluate in a late evaluate phase. The late evaluate phase of the late clock signal commences during the early evaluate phase of the early clock signal and terminates during an early pre-charge phase of the early clock signal in order to artificially induce clock asymmetry to compensate for logic asymmetry in alternating pipeline phases of the dynamic logic circuit.
摘要翻译：一种用于增加包括多个逻辑级的动态逻辑电路的工作频率的评估阶段扩展系统。多个逻辑级被划分成第一组逻辑级，其响应于早期时钟信号，并且在早期评估阶段和第二组逻辑级中进行评估，逻辑级响应迟后时钟信号，并且在迟到评估阶段。晚时钟信号的延迟评估阶段在早期时钟信号的早期评估阶段期间开始，并且在早期时钟信号的早期预充电阶段期间终止，以人为地诱导时钟不对称性来补偿交替流水线相位中的逻辑不对称的动态逻辑电路。

7. 发明授权

US5689228A Parallel magnitude comparison using manchester carry chains 失效
标题翻译：使用曼彻斯特携带链进行平行幅度比较
公开(公告)号：US5689228A
公开(公告)日：1997-11-18
申请号：US731632
申请日：1996-10-15
申请人： Jeffry D. Yetter , Paul L. Perez
发明人： Jeffry D. Yetter , Paul L. Perez
IPC分类号： G06F7/02 , G06F7/76 , G06F9/30
CPC分类号： G06F7/764 , G06F7/026 , G06F9/30021
摘要： Disclosed herein are methods and apparatus for performing magnitude comparisons within a shift-merge unit (SMU). A programmable or partially programmable Manchester carry chain is used to perform each comparison. The Manchester carry chains are programmed using the bits of mask markers and are constructed so as to make a comparison with respect to a given mask condition and position marker which are constants. An implementation in dual rail dynamic CMOS logic avoids the necessity of input inversions, and allows construction of more compact Manchester carry chain circuitry. The size of an SMU will therefore be determined by mask marker routings rather than transistor count. When shorted, opened, and/or redundant transistors, and/or transistors programmed with constants are optimized out of constructed Manchester carry chains, the mask marker bits of a dual rail SMU will have equal fanouts, thereby preventing clock skew. Manchester carry chains may be broken into modular components which may be stepped a number of times to create a 2.sup.N bit SMU. Breaking carry chains into modular components also allows the creation of a single mask, or several smaller masks, within a single SMU. This is an important factor in handling multimedia data which comprises smaller word lengths than instruction data.
摘要翻译：这里公开了用于在移位合并单元（SMU）内执行幅度比较的方法和装置。可编程或部分可编程的曼彻斯特进位链用于执行每个比较。曼彻斯特携带链使用掩码标记的位进行编程，并被构造成与给定的掩模条件和作为常数的位置标记进行比较。双轨动态CMOS逻辑的实现避免了输入反转的必要性，并且允许构建更紧凑的曼彻斯特输入链电路。因此，SMU的尺寸将由掩模标记路由而不是晶体管数量来确定。当由构造的曼彻斯特进位链优化短路，开路和/或冗余晶体管和/或由常数编程的晶体管时，双轨SMU的掩模标记位将具有相等的扇出，从而防止时钟偏移。曼彻斯特携带链可能被分解成模块化组件，可以多次步进，以创建2N位SMU。将携带链分解成模块化组件还允许在单个SMU内创建单个掩模或几个更小的掩模。这是处理多媒体数据的重要因素，其中包括比指令数据更小的字长。

8. 发明申请

US20140316539A1 DRIVERS AND CONTROLLERS 审中-公开
标题翻译：驱动和控制器
公开(公告)号：US20140316539A1
公开(公告)日：2014-10-23
申请号：US14356598
申请日：2012-01-31
申请人： Raju C. Bopardikar , Douglas L. Voigt , Dwight L. Barron , Paul L. Perez
发明人： Raju C. Bopardikar , Douglas L. Voigt , Dwight L. Barron , Paul L. Perez
IPC分类号： G05B15/02
CPC分类号： G05B15/02 , G06F9/4411 , G06F11/2092 , G06F13/102 , G06F13/385 , G06F2213/3802
摘要： Disclosed herein is a technique to transfer at least one unfinished operation from one controller to a second controller, if the first controller has ceased.
摘要翻译：本文公开了一种如果第一控制器已经停止，则将至少一个未完成的操作从一个控制器传送到第二控制器的技术。

9. 发明申请

US20080266726A1 Cooling system for electrical devices 审中-公开
标题翻译：电气设备冷却系统
公开(公告)号：US20080266726A1
公开(公告)日：2008-10-30
申请号：US11796402
申请日：2007-04-27
申请人： Vance Murakami , Christian L. Belady , Paul L. Perez , Robert A. Pereira
发明人： Vance Murakami , Christian L. Belady , Paul L. Perez , Robert A. Pereira
IPC分类号： H02H7/20
CPC分类号： H05K7/2079
摘要： Embodiments include a server and a sensor that detects when a first fluid line to the server fails so a second fluid line to the server is activated.
摘要翻译：实施例包括服务器和传感器，其检测到服务器的第一流体管线何时失效，从而使服务器的第二流体管线被激活。

10. 发明授权

US06456112B1 Method and apparatus for improving signal noise immunity in CMOS dynamic logic circuitry 失效
标题翻译：用于提高CMOS动态逻辑电路中信号噪声抗扰度的方法和装置
公开(公告)号：US06456112B1
公开(公告)日：2002-09-24
申请号：US09207354
申请日：1998-12-08
申请人： Paul L. Perez
发明人： Paul L. Perez
IPC分类号： H03K1900
CPC分类号： H03K19/01728
摘要： A noise suppression circuit is presented which improves signal quality on signal control lines of dynamic logic circuits. The noise suppression circuit provides dynamic line termination and immunity to cross-coupling of signals from other control lines. The line termination portion of the circuit suppresses high-transitioning pulses on low-drive control lines by referencing the low control line level to the local ground and low-transitioning pulses on high-drive control lines by referencing the control line level to a local power supply to immunize pass-gate logic. The input of a CMOS inverter is coupled to the control line. The drain of a FET is coupled to the output control line, and its gate is coupled to the output of the CMOS inverter. Suppression of high-transitioning and low-transitioning pulses is achieved by coupling the source of the FET to the local ground or local power supply respectively. Cross-coupling of signals between the control line and another control line is prevented by cross-coupling a pair of FETs between the two control lines, with the drain of the respective FET coupled to its respective control line and the gate of the respective FET coupled to the other control line.
摘要翻译：提出了一种提高动态逻辑电路信号控制线路信号质量的噪声抑制电路。噪声抑制电路提供动态线路终端和对来自其他控制线路的信号的交叉耦合的抗扰性。电路的线路终端部分通过将控制线电平参考到局部功率来参考低驱动控制线上的低控制线电平和高驱动控制线上的低转换脉冲来抑制低驱动控制线上的高转换脉冲供应免疫传递门逻辑。 CMOS反相器的输入耦合到控制线。 FET的漏极耦合到输出控制线，并且其栅极耦合到CMOS反相器的输出端。通过将FET的源极分别耦合到局部接地或局部电源来实现高转换和低转换脉冲的抑制。通过在两个控制线之间交叉耦合一对FET来防止控制线与另一控制线之间的信号的交叉耦合，其中各个FET的漏极耦合到其相应的控制线，并且相应FET的栅极耦合到另一个控制线。

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