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1. 发明申请

US20130009276A1 METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES 审中-公开
标题翻译：填充半导体器件和结构结构的隔离条件的方法
公开(公告)号：US20130009276A1
公开(公告)日：2013-01-10
申请号：US13616199
申请日：2012-09-14
申请人： Paul J. Rudeck , Sukesh Sandhu
发明人： Paul J. Rudeck , Sukesh Sandhu
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique.
摘要翻译：本发明涉及一种在典型的沟槽形状和球柱形隔离区域的隔离沟槽隔离填充过程中基本上最小化和/或消除空隙形成的方法和结果。首先，在每个沟槽的侧壁上生长薄的热氧化层，然后在氧化层上方沉积一层多晶硅并被氧化。在一个实施例中，执行重复的多晶硅沉积和多晶硅氧化步骤，直到每个沟槽已经被完全填充。在另一个实施例中，在具有较宽上部和较窄下部的球柱形沟槽内，使用常规高密度等离子体技术填充上部较宽沟槽部分的其余部分。

2. 发明授权

US07212435B2 Minimizing adjacent wordline disturb in a memory device 有权
标题翻译：最小化存储设备中的相邻字线干扰
公开(公告)号：US07212435B2
公开(公告)日：2007-05-01
申请号：US10881951
申请日：2004-06-30
申请人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
发明人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.
摘要翻译：耦合到用于编程的单元的所选字线被编程电压偏置。与所选字线相邻的未选字线被偏置在第一预定电压。剩余的字线被偏置在大于第一预定电压的第二预定电压。通过确定什么未选择的相邻字线偏置电压响应于所选择的字线编程电压产生最小化的Vcc通道干扰来选择第一预定电压。

3. 发明授权

US06756268B2 Modified source/drain re-oxidation method and system 失效
标题翻译：改性源/漏再氧化法和体系
公开(公告)号：US06756268B2
公开(公告)日：2004-06-29
申请号：US10143450
申请日：2002-05-10
申请人： Paul J. Rudeck , Francis Benistant , Kelly Hurley
发明人： Paul J. Rudeck , Francis Benistant , Kelly Hurley
IPC分类号： H01L21336
CPC分类号： H01L21/02129 , H01L21/022 , H01L21/0234 , H01L21/31625 , H01L27/115 , H01L27/11521 , H01L29/6659 , H01L29/66659 , H01L29/66825
摘要： Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.
摘要翻译：公开了利用在再氧化之前加入的磷掺杂氧化物层的方法和装置。这允许更好地控制再氧化过程并且更好地控制诸如闪存之类的半导体器件的性能特性。对于闪存，可以在编程速率，擦除速率，数据保留和自对准源电阻方面获得更大的控制。

4. 发明授权

US06577537B2 Flash memory cell for high efficiency programming 有权
公开(公告)号：US06577537B2
公开(公告)日：2003-06-10
申请号：US10205700
申请日：2002-07-26
申请人： Andrei Mihnea , Paul J. Rudeck , Chun Chen
发明人： Andrei Mihnea , Paul J. Rudeck , Chun Chen
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

5. 发明授权

US06566195B2 Method and structure for an improved floating gate memory cell 有权
公开(公告)号：US06566195B2
公开(公告)日：2003-05-20
申请号：US10068198
申请日：2002-02-06
申请人： Paul J. Rudeck
发明人： Paul J. Rudeck
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory cell also includes a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. The memory cell further includes a second insulating layer formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region. Arrays, memory devices, and systems are further included in the scope of the present invention.

6. 发明授权

US06445620B2 Flash memory cell for high efficiency programming 有权
标题翻译：闪存单元，用于高效率编程
公开(公告)号：US06445620B2
公开(公告)日：2002-09-03
申请号：US09920465
申请日：2001-08-01
申请人： Andrei Mihnea , Paul J. Rudeck , Chun Chen
发明人： Andrei Mihnea , Paul J. Rudeck , Chun Chen
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
摘要翻译：闪存单元包括栅极，漏极，源极，浮动栅极和控制栅极。通过向栅极施加第一电压，向漏极施加第二电压，并且通过向漏极施加第三电压，通过在深耗尽区域上诱导约四伏和六伏之间的电压降来对闪存单元进行编程资源。在编程操作期间，通道电流近似为零，并且第一电压以与注入电流成比例的速率斜坡化。

7. 发明授权

US07294567B2 Semiconductor contact device and method 有权
标题翻译：半导体接触器件及方法
公开(公告)号：US07294567B2
公开(公告)日：2007-11-13
申请号：US10095274
申请日：2002-03-11
申请人： Paul J. Rudeck
发明人： Paul J. Rudeck
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L29/513
摘要： The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.
摘要翻译：本发明提供了用于在衬底上制造存储单元阵列的高级金属化技术。通过在布置在阵列上的第一层中形成离散的和自对准的通孔来形成阵列，以形成与阵列中的每个源极和漏极结的接触。此外，自对准局部开槽的通孔形成在布置在第一层上的第二层中，以形成电分流所有源极触点/结的局部互连。此外，在每个形成的漏极接触件上方形成离散的自对准漏极延伸部，以将连接点和源极触点电连接到延伸部分。形成的通孔，延伸部分和开槽局部通孔同时被插入并填充有导电材料以形成存储单元阵列。

8. 发明授权

US07148547B2 Semiconductor contact device 有权
标题翻译：半导体接触器件
公开(公告)号：US07148547B2
公开(公告)日：2006-12-12
申请号：US10929634
申请日：2004-08-30
申请人： Paul J. Rudeck
发明人： Paul J. Rudeck
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L29/513
摘要： The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.
摘要翻译：本发明提供了用于在衬底上制造存储单元阵列的高级金属化技术。通过在布置在阵列上的第一层中形成离散的和自对准的通孔来形成阵列，以形成与阵列中的每个源极和漏极结的接触。此外，自对准局部开槽的通孔形成在布置在第一层上的第二层中，以形成电分流所有源极触点/结的局部互连。此外，在每个形成的漏极接触件上方形成离散的自对准漏极延伸部，以将连接点和源极触点电连接到延伸部分。形成的通孔，延伸部分和开槽局部通孔同时被插入并填充有导电材料以形成存储单元阵列。

9. 发明授权

US06713350B2 Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack 有权
标题翻译：当氮化物空间形成从围绕栅极堆叠的氧化物衬里开始时，沿栅极堆叠边缘去除氧化物接缝的方法
公开(公告)号：US06713350B2
公开(公告)日：2004-03-30
申请号：US10213086
申请日：2002-08-07
申请人： Paul J. Rudeck
发明人： Paul J. Rudeck
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.
摘要翻译：去除暴露的垂直氧化物间隔物的顶端，并且在将存储器件暴露于自对准接触蚀刻工艺之前，以足以代替去除的部分的量沉积氮化物层。氮化物层可以用于防止通过氧化物间隔物的短路。本发明还提供了一种存储器件，它们具有一个栅极叠层，一个邻近栅极叠层的垂直隔离层，其中垂直间隔物具有一个包含一个氧化物的下部分和一个包含一个氮化物的上部分，以及一个连续的氮化物层，间隔器和栅极堆叠。本发明还提供了制造上述装置的方法以及包括这些装置的处理器系统。

10. 发明授权

US06611019B2 Method and structure for an improved floating gate memory cell 有权
公开(公告)号：US06611019B2
公开(公告)日：2003-08-26
申请号：US10068698
申请日：2002-02-06
申请人： Paul J. Rudeck
发明人： Paul J. Rudeck
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory cell also includes a shallow trench isolation (STI) region having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. The memory cell further includes a second insulating layer formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region. Arrays, memory devices, and systems are further included in the scope of the present invention.

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