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1. 发明授权

US5097331A Multiple block-size transform video coding using an asymmetric sub-band structure 失效
标题翻译：使用非对称子带结构的多块大小变换视频编码
公开(公告)号：US5097331A
公开(公告)日：1992-03-17
申请号：US573242
申请日：1990-08-24
申请人： Ting-Chung Chen , Paul E. Fleischer
发明人： Ting-Chung Chen , Paul E. Fleischer
IPC分类号： G06F17/14 , H03H17/02 , H04N7/26 , H04N7/30
CPC分类号： H04N19/60 , G06F17/145 , H03H17/0266 , H04N19/63 , H04N19/635 , H04N19/42
摘要： A sub-band coder for video signals is disclosed, which is easily realizable in VLSI due to its simple structure. The coder uses sets of two-tap finite impulse response (FIR) filters having equal-magnitude coefficients to decompose the video signal at multiple stages. In the preferred embodiment the sub-band coder has an asymmetrical structure. With the arrangement, the sub-band decomposition effects what is equivalent to a multiple block-size Hadamard transform of the video signal in which coefficients are transmitted from various block-sized transforms of larger blocks of pixel data.
摘要翻译：公开了一种用于视频信号的子带编码器，其由于其简单的结构而容易在VLSI中实现。编码器使用具有等幅度系数的两抽头有限脉冲响应（FIR）滤波器集合来分解多级的视频信号。在优选实施例中，子带编码器具有不对称结构。通过该配置，子带分解效果相当于视频信号的多块大小Hadamard变换，其中系数从较大的像素数据块的各种块大小的变换发送。

2. 再颁专利

USRE36633E Synchronous residual time stamp for timing recovery in a broadband network 失效
标题翻译：用于宽带网络定时恢复的同步剩余时间戳
公开(公告)号：USRE36633E
公开(公告)日：2000-03-28
申请号：US555196
申请日：1995-11-08
申请人： Paul E. Fleischer , Chi-Leung Lau
发明人： Paul E. Fleischer , Chi-Leung Lau
IPC分类号： H04J3/06 , H04L12/56 , H04L12/64 , H04N21/43 , H04N21/643 , H04Q11/04 , H04L7/00
CPC分类号： H04N21/64307 , H04J3/0632 , H04L12/6418 , H04N21/4305 , H04Q11/0478 , H04L2012/5649 , H04L2012/5653 , H04L2012/5654 , H04L2012/5674
摘要： A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2.sub.P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range. At the destination node, a pulse signal is derived in which the periods are determined by the number of network clock cycles represented by the received RTSs. This pulse signal is then multiplied in frequency by N to recover the source node service clock.
摘要翻译：残余时间戳（RTS）技术提供了一种在同步ATM电信网络的目的地节点处恢复恒定比特率输入服务信号的定时信号的方法和装置。在源节点，自由运行的P位计数器在公共网络时钟中计数周期。在由N个服务时钟周期形成的每个RTS周期结束时，定义为RTS的P位计数器的当前计数在ATM适配层中传输。由于可能落在RTS周期内的网络时钟周期的绝对数量将落在由N确定的范围内，因此选择网络和服务时钟的频率以及服务时钟P的容限，使得2P可能计数，而不是表示RTS周期的网络时钟周期的绝对数量，提供足够的信息来明确地表示在该预定范围内的网络时钟周期的数量。在目的地节点处，导出脉冲信号，其中周期由接收的RTS表示的网络时钟周期的数量确定。然后将该脉冲信号以频率乘以N以恢复源节点服务时钟。

3. 发明授权

US4315227A Generalized switched-capacitor active filter 失效
标题翻译：广义开关电容有源滤波器
公开(公告)号：US4315227A
公开(公告)日：1982-02-09
申请号：US100293
申请日：1979-12-05
申请人： Paul E. Fleischer , Kenneth R. Laker
发明人： Paul E. Fleischer , Kenneth R. Laker
IPC分类号： H03F3/00 , H03H19/00 , H03K5/153
CPC分类号： H03H19/004 , H03F3/005
摘要： Because of the very large variety of useful filter configurations, it is highly desirable to have a generalized circuit topology from which all specific filters can be derived. A generalized switched-capacitor biquadratic active filter comprises a pair of operational amplifiers (10, 11), each of which has an unswitched feedback capacitor (D, B) connected between its output port (3, 3') and its inverting input port (1, 1'). A third through-switched capacitor (C) provides feedback between the output port (3') of the second amplifier (11) and the inverting input port (1) of the first amplifier (10). A diagonally-switched capacitor (A) couples the output port (3) of the first amplifier (10) to the inverting input port (1') of the second amplifier (11). The noninverting input ports (2, 2') of the two amplifiers are connected to signal ground. The filter input terminal (5) is connected to the inverting input ports (1, 1') of each amplifier by an input circuit including a parallel array of an unswitched capacitor, a diagonally-switched capacitor, and a through-switched capacitor (L, H, G and K, J, I). Damping is provided by either a through-switched capacitor (F) connected in parallel with feedback capacitor (B), or by a unswitched capacitor (E) connected in parallel with through switched feedback capacitor (C).
摘要翻译：由于有用的滤波器配置的种类非常多，所以非常希望有一个广义的电路拓扑，从中可以推导出所有特定的滤波器。广义开关电容器二元有源滤波器包括一对运算放大器（10,11），每对运算放大器具有连接在其输出端口（3,3'）和其反相输入端口（3，3'）之间的非开关反馈电容器（D，B） 1，1'）。第三贯通开关电容器（C）在第二放大器（11）的输出端口（3'）和第一放大器（10）的反相输入端口（1）之间提供反馈。对角线开关电容器（A）将第一放大器（10）的输出端口（3）耦合到第二放大器（11）的反相输入端口（1'）。两个放大器的同相输入端口（2,2'）连接到信号地。滤波器输入端子（5）通过包括未开关电容器，对角线开关电容器和贯通开关电容器（L）的并联阵列的输入电路连接到每个放大器的反相输入端口（1,1'），H，G和K，J，I）。通过与反馈电容器（B）并联连接的通过开关电容器（F）或与通过开关反馈电容器（C）并联连接的未开关电容器（E）提供阻尼。

4. 发明授权

US4492935A Switched capacitor oscillator formed by a damped resonator with saturable feedback 失效
标题翻译：开关电容振荡器由具有可饱和反馈的阻尼谐振器形成
公开(公告)号：US4492935A
公开(公告)日：1985-01-08
申请号：US474685
申请日：1983-03-11
申请人： Paul E. Fleischer , Apparajan Ganesan , Kenneth R. Laker
发明人： Paul E. Fleischer , Apparajan Ganesan , Kenneth R. Laker
IPC分类号： H03B5/02 , H03B5/06 , H03B5/08 , H03C1/00 , H03C3/00
CPC分类号： H03B5/06
摘要： A switched capacitor oscillator is constructed by providing a damped resonator network with a comparator as a nonlinear feedback element by connecting the input of the comparator to the output of a first operational amplifier of the resonator network and connecting the output of the comparator to the input of the resonator network. The comparator thus becomes a saturable positive feedback element for the resonator network. Also disclosed is a startup network for the oscillator and an input network which derives an input from a reference voltage in order to eliminate supply voltage noise and provide precision control of amplitude.
摘要翻译：通过将比较器的输入连接到谐振器网络的第一运算放大器的输出并将比较器的输出连接到比较器的输入端，将具有比较器的阻尼谐振器网络提供为非线性反馈元件构成开关电容振荡器谐振器网络。因此，比较器成为谐振器网络的可饱和正反馈元件。还公开了用于振荡器的启动网络和从参考电压导出输入的输入网络，以便消除电源电压噪声并提供振幅的精确控制。

5. 发明授权

US5260978A Synchronous residual time stamp for timing recovery in a broadband network 失效
标题翻译：用于宽带网络定时恢复的同步剩余时间戳
公开(公告)号：US5260978A
公开(公告)日：1993-11-09
申请号：US969592
申请日：1992-10-30
申请人： Paul E. Fleischer , Chi-Leung Lau
发明人： Paul E. Fleischer , Chi-Leung Lau
IPC分类号： H04J3/06 , H04L12/56 , H04L12/64 , H04N21/43 , H04N21/643 , H04Q11/04 , H04L7/00
CPC分类号： H04N21/64307 , H04J3/0632 , H04L12/6418 , H04N21/4305 , H04Q11/0478 , H04L2012/5649 , H04L2012/5653 , H04L2012/5654 , H04L2012/5674
摘要： A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2.sup.P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range. At the destination node, a pulse signal is derived in which the periods are determined by the number of network clock cycles represented by the received RTSs. This pulse signal is then multiplied in frequency by N to recover the source node service clock.
摘要翻译：残余时间戳（RTS）技术提供了一种在同步ATM电信网络的目的地节点处恢复恒定比特率输入服务信号的定时信号的方法和装置。在源节点，自由运行的P位计数器在公共网络时钟中计数周期。在由N个服务时钟周期形成的每个RTS周期结束时，定义为RTS的P位计数器的当前计数在ATM适配层中传输。由于可能落在RTS周期内的网络时钟周期的绝对数量将落在由N确定的范围内，因此选择网络和服务时钟的频率以及服务时钟P的容限，使得2P可能计数，而不是表示RTS周期的网络时钟周期的绝对数量，提供足够的信息来明确地表示在该预定范围内的网络时钟周期的数量。在目的地节点处，导出脉冲信号，其中周期由接收的RTS表示的网络时钟周期的数量确定。然后将该脉冲信号以频率乘以N以恢复源节点服务时钟。

6. 发明授权

US4399417A Integrated CRC filter circuit 失效
标题翻译：集成CRC滤波电路
公开(公告)号：US4399417A
公开(公告)日：1983-08-16
申请号：US157452
申请日：1980-06-06
申请人： James P. Ballantyne , Paul E. Fleischer , Kenneth R. Laker , Aristides A. Yiannoulos
发明人： James P. Ballantyne , Paul E. Fleischer , Kenneth R. Laker , Aristides A. Yiannoulos
IPC分类号： H01L27/07 , H03H11/12 , H01L29/94 , H01L27/04 , H03H7/01
CPC分类号： H03H7/0123 , H01L27/0794 , H03H1/02 , H03H11/1204
摘要： A capacitor-resistor-capacitor (CRC) element for active filter realization, which is fully integrable and compatible with MOS technology, is described. The incorporation of the CRC element in a semiconductor integrated circuit active filter also is described. The structure of the CRC filter element is closely analogous to a depletion mode MOS field effect device, except that the channel zone 26 is doped to a level which substantially precludes conductivity modulation at the usual operating voltages. However, the doping level is such as to enable the use of the channel zone as a semiconductor resistance element. Thus, the N-channel CRC element realized in the NMOS technology comprises a first capacitance composed of the gate 27, gate dielectric 38, and resistive channel 26, paralleled by the resistive channel 26 itself constituting a resistor, and then the underlying PN junction capacitance between the N-type resistive channel 26 and the underlying P-type semiconductor body portion 21. An active low-pass filter consists of two CRC elements and an operational amplifier and utilizes the positive feedback principle.
摘要翻译：描述了用于有源滤波器实现的电容器 - 电阻 - 电容（CRC）元件，其完全可集成并且与MOS技术兼容。还描述了将CRC元件结合到半导体集成电路有源滤波器中。 CRC滤波器元件的结构非常类似于耗尽型MOS场效应器件，不同之处在于通道区26被掺杂到基本上阻止在通常工作电压下的电导率调制的水平。然而，掺杂水平使得能够使用沟道区作为半导体电阻元件。因此，在NMOS技术中实现的N沟道CRC元件包括由栅极27，栅极电介质38和电阻通道26组成的第一电容，其由构成电阻器的电阻通道26本身并联，然后是下面的PN结电容 N型电阻通道26与下面的P型半导体主体部分21之间。有源低通滤波器由两个CRC元件和运算放大器组成，并利用正反馈原理。

7. 发明授权

US4313096A Parasitic-free switched capacitor network 失效
标题翻译：无寄生开关电容网络
公开(公告)号：US4313096A
公开(公告)日：1982-01-26
申请号：US95663
申请日：1979-11-19
申请人： Paul E. Fleischer
发明人： Paul E. Fleischer
IPC分类号： H03H19/00
CPC分类号： H03H19/004
摘要： Switched capacitor topologies currently in use are susceptible to the deleterious effects of the parasitic capacitances associated with the switches. Topologies that are immune to these effects are disclosed. A first such embodiment comprises a first switch (22, 32), a capacitor (23, 33), and a second switch (24, 34) connected in series between one input terminal (1) and one output terminal (3) of the network. Third and fourth switches (26, 35 and 27, 36) are connected between the junctions (98, 42 and 99, 43) of the capacitor and the first and second switches, respectively, and the common junction (97, 41) of the second input and second output terminals (2, 4). A second embodiment is also disclosed.
摘要翻译：目前使用的开关电容器拓扑容易受到与开关相关联的寄生电容的有害影响。公开了免疫这些影响的拓扑。第一个这样的实施例包括串联连接在一个输入端（1）和一个输出端（3）之间的第一开关（22,32），电容器（23,33）和第二开关（24,34）网络。第三和第四开关（26,35和27,36）分别连接在电容器和第一和第二开关的接点（98,42和99,43）之间，并且公共接头（97,41）第二输入端和第二输出端子（2,4）。还公开了第二实施例。

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