会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Method and apparatus for realignment of synchronous data
    • 用于重新对准同步数据的方法和装置
    • US5359630A
    • 1994-10-25
    • US929623
    • 1992-08-13
    • Paul C. WadeDavid J. SagerAndrey Varpahovsky
    • Paul C. WadeDavid J. SagerAndrey Varpahovsky
    • G06F1/10H04L7/00H04L7/033H04L7/04
    • G06F1/10H04L7/0012H04L7/0338
    • A method and device for receiving data in a synchronous communication system. Data can be accurately transferred between two subsystems in a synchronous system even where the clock skew and propagation delay between the two subsystems is unlimited. The receiving subsystem is initialized to ensure synchronous data transfer over a theoretically infinite range. The transmitting subsystem transmits data and a forwarded clock to the receiving subsystem. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the clock of the receiving subsystem by controlling a multiplexer which selects the proper state device output to pass to another state device for alignment to the receiving subsystem's clock. The multiplexer is controlled by a circuit which monitors the capturing of the incoming data and determines the correct state device output to select for proper data alignment.
    • 一种用于在同步通信系统中接收数据的方法和装置。 即使在两个子系统之间的时钟偏移和传播延迟是无限制的情况下,也可以在同步系统中的两个子系统之间精确地传输数据。 接收子系统被初始化以确保在理论上无限范围内的同步数据传输。 发送子系统向接收子系统发送数据和转发时钟。 在并行布置的三个状态设备中捕获数据,以消除最小延迟要求并扩展数据有效时间。 捕获的数据然后通过控制多路复用器对准接收子系统的时钟,多路复用器选择适当的状态设备输出传递到另一个状态设备以与接收子系统的时钟对准。 多路复用器由监视输入数据的捕获的电路控制,并确定正确的状态设备输出以选择正确的数据对准。
    • 7. 发明授权
    • High-power, high-performance integrated circuit chip package
    • 大功率,高性能的集成电路芯片封装
    • US5068715A
    • 1991-11-26
    • US546569
    • 1990-06-29
    • Paul C. WadeJJ Grady, III
    • Paul C. WadeJJ Grady, III
    • H01L23/04H01L23/051H01L23/36
    • H01L23/04H01L23/051H01L23/36H01L2924/0002H01L2924/01079H01L2924/3011
    • The high-power, high-performance integrated circuit chip package comprises a chip constructed to contain top and bottom surfaces to which top and bottom metallization planes are fixed. Top and bottom heat sinks are fixedly mounted to the top metallization plane and bottom metallization plane, respectively. The metallization planes and heat sink combination functions as both a power lead and a heat dissipation means, allowing for the chip to contain signal connections which may be dedicated to input and output signal paths. The chip further comprises a plurality of contiguous top layers of thin dielectric material, at least one epitaxial layer on whichis mounted a plurality of transistors and associated circuitry, and at least one bottom layer of crystalline silicon material. The plurality of transistors and associated circuitry generates heat. Such heat may then be dissipated by following a first or second thermal path, the first path proceeding through the plurality of contiguous top layers, through the top metallization plane to the top heat sink and the second thermal path proceeding through at least one bottom layer through the bottom metallization plane to the bottom heat sink.
    • 大功率,高性能的集成电路芯片封装包括一个构造成容纳顶部和底部金属化平面固定的顶表面和底表面的芯片。 顶部和底部散热器分别固定地安装在顶部金属化平面和底部金属化平面上。 金属化平面和散热器组合既用作电源引线又用作散热装置,从而允许芯片包含专用于输入和输出信号路径的信号连接。 芯片还包括多个连续的薄介电材料的顶层,至少一个外延层上安装有多个晶体管和相关电路,以及至少一个结晶硅材料的底层。 多个晶体管和相关电路产生热量。 然后可以通过跟随第一或第二热路径,第一路径穿过多个相邻顶层,穿过顶部金属化平面到顶部散热器,并且第二热路径通过至少一个底层通过 底部金属化平面到底部散热器。