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1. 发明授权

US09619855B2 Scalable geometry processing within a checkerboard multi-GPU configuration 有权
公开(公告)号：US09619855B2
公开(公告)日：2017-04-11
申请号：US13976843
申请日：2011-11-18
申请人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
发明人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
IPC分类号： G06T15/00 , G06T1/20 , G06T15/10
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

2. 发明授权

US07348986B2 Image rendering 有权
标题翻译：图像渲染
公开(公告)号：US07348986B2
公开(公告)日：2008-03-25
申请号：US11045018
申请日：2005-01-26
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F15/16 , G06F15/80
CPC分类号： G06T1/20
摘要： An image is rendered by dividing the image into chunks, rendering the chunks in one of at least two devices, and determining which of the devices renders each one of at least some of the chunks based on at least one device's progress in the rendering of other chunks.
摘要翻译：通过将图像划分成多个块来呈现图像，将块分解成至少两个设备中的一个，并且基于至少一个设备在渲染另一个设备中的进度来确定哪个设备呈现至少一些块中的每一个块

3. 发明授权

US06885374B2 Apparatus, method and system with a graphics-rendering engine having a time allocator 有权
公开(公告)号：US06885374B2
公开(公告)日：2005-04-26
申请号：US09895529
申请日：2001-06-29
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F3/14 , G06T15/00 , G06T17/00 , G06F15/80
CPC分类号： G06F3/1431 , G06T15/005
摘要： A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

4. 发明授权

US06747658B2 Automatic memory management for zone rendering 有权
标题翻译：区域渲染的自动内存管理
公开(公告)号：US06747658B2
公开(公告)日：2004-06-08
申请号：US10038921
申请日：2001-12-31
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G09G536
CPC分类号： G06T1/60 , G06T15/04
摘要： The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
摘要翻译：本发明通过在分箱和渲染阶段之间提供bin存储器的自动管理来优化区域渲染期间的图形性能。本发明的实施例提供了一种机制，通过该机制，虚拟机和渲染器自动共享物理存储器页面池，以便构建bin缓冲器并在渲染后使用它们。这样做的方式是，可以将多个分箱的场景同时排队，除非在特殊情况下不需要软件干预。因此消除了对区域渲染bin缓冲存储器的软件管理的需要。用于分档和渲染的多个场景也可以排队等待，无需软件干预。

5. 发明授权

US06747653B2 Efficient object storage for zone rendering 有权
标题翻译：用于区域渲染的高效对象存储
公开(公告)号：US06747653B2
公开(公告)日：2004-06-08
申请号：US10039006
申请日：2001-12-31
申请人： Peter L. Doyle
发明人： Peter L. Doyle
IPC分类号： G06F1500
CPC分类号： G06T15/005
摘要： Similar, contiguous primitives are stored as a single primitive in zone rendering bins. A primitive packet used in the bin is allowed to vary in length and the currently open type of primitive is recorded on a per-bin basis. A special code is used to specify a variable number of subsequent indices. With this mechanism, the hardware is able to start outputting and replicating primitive commands into bin lists on the fly without requiring the buffering of the entire primitive. Given the variable nature of the primitive instruction, multiple similar/sequential primitives can be concatenated using a single primitive command header.
摘要翻译：类似的连续原语作为单个基元存储在区域渲染区域中。允许在箱中使用的原始包在长度上变化，并且当前打开的原语类型以每个箱为单位被记录。特殊代码用于指定可变数量的后续索引。利用这种机制，硬件能够在不需要缓冲整个原语的情况下开始将原始命令输出和复制到bin列表中。给定基本指令的可变性质，可以使用单个基元命令头连接多个相似/顺序图元。

6. 发明授权

US06731297B1 Multiple texture compositing 失效
标题翻译：多重纹理合成
公开(公告)号：US06731297B1
公开(公告)日：2004-05-04
申请号：US09885253
申请日：2000-01-11
申请人： Kam Leung , Val G. Cook , Peter L. Doyle , Wing Hang Wong
发明人： Kam Leung , Val G. Cook , Peter L. Doyle , Wing Hang Wong
IPC分类号： G09G500
CPC分类号： G06T15/04 , G06T11/001 , G06T15/005
摘要： A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.
摘要翻译：一种包含可执行程序指令的机器可读存储介质，其在被执行时使数字处理系统设置多个操作数和操作符。将多个纹理贴图发送到处理器以进行纹理合成。为纹理操作选择操作数。使用第一逻辑，其中如果混合阶段的循环等于混合阶段的数量，则执行颜色饱和度，以及第二逻辑，如果混合阶段的循环数量不等于混合阶段的数量，则在为另一个纹理合成操作选择最少一个操作数。

7. 发明授权

US5097411A Graphics workstation for creating graphics data structure which are stored retrieved and displayed by a graphics subsystem for competing programs 失效
标题翻译：用于创建由用于竞争程序的图形子系统检索和显示的图形数据结构的图形工作站
公开(公告)号：US5097411A
公开(公告)日：1992-03-17
申请号：US258398
申请日：1988-10-17
申请人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. Dipirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
发明人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. Dipirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
IPC分类号： G06T17/00
CPC分类号： G06T17/00
摘要： A method for operating a computer graphics system to build custom nodes containing commands and data information that is stored in a data structure in the graphics subsystem. A host processor calls routines which build the custome nodes. A structure walker traverses the data structure and extracts the information from the data structure to pass it to the graphics subsystem for display. The use of custom nodes increases the flexibility of advanced graphics data structures bny allowing the creation of other data structures during execution of a first data structure.
摘要翻译：一种用于操作计算机图形系统以构建包含存储在图形子系统中的数据结构中的命令和数据信息的定制节点的方法。主机处理器调用构建客户端节点的例程。结构步行者遍历数据结构，并从数据结构中提取信息，将其传递给图形子系统进行显示。使用自定义节点增加了高级图形数据结构的灵活性，允许在执行第一个数据结构期间创建其他数据结构。

8. 发明申请

US20190066354A1 APPARATUS AND METHOD FOR PROCESSING COMMANDS IN TILE-BASED RENDERERS 审中-公开
公开(公告)号：US20190066354A1
公开(公告)日：2019-02-28
申请号：US15692951
申请日：2017-08-31
申请人： HEMA C. NALLURI , BALAJI VEMBU , PETER L. DOYLE , MICHAEL APODACA , JEFFERY S. BOLES
发明人： HEMA C. NALLURI , BALAJI VEMBU , PETER L. DOYLE , MICHAEL APODACA , JEFFERY S. BOLES
IPC分类号： G06T15/00 , G06T17/10 , G06T7/507 , G06T15/30 , G06T1/60
摘要： An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.

9. 发明申请

US20180082465A1 APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING 审中-公开
公开(公告)号：US20180082465A1
公开(公告)日：2018-03-22
申请号：US15268496
申请日：2016-09-16
申请人： PRASOONKUMAR SURTI , TOMAS G. AKENINE-MOLLER , DAVID COWPERTHWAITE , KEVIN TIAN , PETER L. DOYLE , BRENT INSKO , ADAM T. LAKE
发明人： PRASOONKUMAR SURTI , TOMAS G. AKENINE-MOLLER , DAVID COWPERTHWAITE , KEVIN TIAN , PETER L. DOYLE , BRENT INSKO , ADAM T. LAKE
IPC分类号： G06T15/00 , G06T1/60 , G06T1/20 , G06T15/40 , G06T15/50
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T15/405 , G06T15/503 , G06T2207/20021 , G06T2210/12
摘要： A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

10. 发明申请

US20180082464A1 APPARATUS AND METHOD FOR AN EFFICIENT 3D GRAPHICS PIPELINE 审中-公开
公开(公告)号：US20180082464A1
公开(公告)日：2018-03-22
申请号：US15268495
申请日：2016-09-16
申请人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , BRENT E. INSKO , PETER L. DOYLE , PRASOONKUMAR SURTI , MAIYURAN SUBRAMANIAM , CARL JACOB MUNKBERG , FRANZ PETRIK CLARBERG , JON N. HASSELGREN
发明人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , BRENT E. INSKO , PETER L. DOYLE , PRASOONKUMAR SURTI , MAIYURAN SUBRAMANIAM , CARL JACOB MUNKBERG , FRANZ PETRIK CLARBERG , JON N. HASSELGREN
IPC分类号： G06T15/00 , G06T17/10 , G06T15/80 , G06T15/30 , G06T15/40 , G06T17/20 , G06T15/04 , G06T15/20
CPC分类号： G06T15/005 , G06T15/04 , G06T15/205 , G06T15/30 , G06T15/405 , G06T15/80 , G06T17/10 , G06T17/20 , G06T2210/12
摘要： A graphics processing apparatus and method are described. For example, one embodiment of a graphics processing apparatus comprises: an input assembler of a graphics pipeline to determine a first set of triangles to be drawn based on application-provided parameters; a depth buffer to store depth data related to the first set of triangles; a vertex shader to perform position-only vertex shading operations on the first set of triangles in response to an indication that the graphics pipeline is to initially operate in a depth-only mode; a culling and clipping module to read depth values from the depth buffer to identify those triangles in the first set of triangles which are fully occluded by other objects in a current frame and to generate culling data usable to cull occluded triangles, the culling and clipping module to associate the culling data with a replay token to be used to identify a subsequent rendering pass through the graphics pipeline; the input assembler, upon detecting the replay token in the subsequent rendering pass, to access the culling data associated therewith to remove culled triangles from the first set of triangles to generate a second set of triangles; the vertex shader to perform full vertex shading operations on the second set of triangles during the subsequent rendering pass, the replay token to be destroyed during or following the subsequent rendering pass.

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