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1. 发明授权

US08402328B2 Apparatus and method for protecting soft errors 有权
标题翻译：用于保护软错误的装置和方法
公开(公告)号：US08402328B2
公开(公告)日：2013-03-19
申请号：US12509019
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
IPC分类号： G01R31/28
CPC分类号： G01R31/31816 , G01R31/318544 , G06F17/505 , G06F2217/14
摘要： An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
摘要翻译：用于进行制造测试操作，慢速快照操作，慢速签名分析操作，速度特征分析操作，缺陷容差操作或缺陷容错操作的能力的软错误恢复或校正的装置和方法以上操作的任意组合。在一个实施例中，一种装置包括用于软错误弹性的系统电路，阴影电路和输出接合电路。耦合到系统电路和阴影电路的输出端子的输出接合电路至少包括用于缺陷容限的S元件。在另一个实施例中，一种装置包括系统电路，阴影电路，调试电路和用于软错误校正的输出连接电路。耦合到系统电路，阴影电路和调试电路的输出端子的输出接合电路至少包括用于缺陷容差的V元件。

2. 发明申请

US20110258501A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 有权
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20110258501A1
公开(公告)日：2011-10-20
申请号：US13172046
申请日：2011-06-29
申请人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
发明人： Nur A. TOUBA , Laung-Terng WANG , Zhigang JIANG , Shianling WU , Jiangping YAN
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

3. 发明申请

US20110047426A1 METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION 有权
标题翻译：低密码扫描压缩的方法和装置
公开(公告)号：US20110047426A1
公开(公告)日：2011-02-24
申请号：US12546060
申请日：2009-08-24
申请人： Nur A. TOUBA , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. TOUBA , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

4. 发明授权

US08949299B2 Method and apparatus for hybrid ring generator design 有权
标题翻译：混合环形发电机设计方法与装置
公开(公告)号：US08949299B2
公开(公告)日：2015-02-03
申请号：US13195524
申请日：2011-08-01
申请人： Laung-Terng Wang , Nur A. Touba
发明人： Laung-Terng Wang , Nur A. Touba
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.
摘要翻译：一种使用低硬件成本的混合环形发生器产生伪随机序列的方法和装置。当选择GF（2）上的原始多项式作为特征多项式f（x）构建混合环形发生器时，实现f（x）的电路将产生最大长度序列（m序列）。混合环形发生器与现有的基于最大长度序列发生器（MLSG）的线性反馈移位寄存器（LFSR）相比具有无与伦比的优势。假设在标准或模块化LFSR设计中需要k个2输入XOR门。这些优点包括仅需要（k + 1）/ 2个2输入异或门，在任何一对触发器之间具有至多一个2输入异或门电平，使每个触发器的输出最多驱动 2个扇出节点，并创建一个高度规则的结构，使新的设计更加布局和时间友好。

5. 发明授权

US07945833B1 Method and apparatus for pipelined scan compression 有权
标题翻译：流水线扫描压缩方法和装置
公开(公告)号：US07945833B1
公开(公告)日：2011-05-17
申请号：US11889710
申请日：2007-08-15
申请人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
发明人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括一个解压缩器，它包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。解压缩器在其压缩的扫描输入端解压缩压缩的扫描图案，并将解压缩器的输出端上产生的解压缩扫描图案驱动到基于扫描的集成电路的扫描数据输入端。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

6. 发明授权

US6061818A Altering bit sequences to contain predetermined patterns 失效
标题翻译：改变位序列以包含预定模式
公开(公告)号：US6061818A
公开(公告)日：2000-05-09
申请号：US074848
申请日：1998-05-08
申请人： Nur A. Touba , Edward J. McCluskey
发明人： Nur A. Touba , Edward J. McCluskey
IPC分类号： G01R31/3185 , G01R31/28 , G06F11/00
CPC分类号： G01R31/318385 , G01R31/318547
摘要： A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.
摘要翻译：内置扫描数字设计的内置自检的低开销方案允许完全（100％）的故障覆盖，而无需修改功能逻辑，而不降低系统性能（超出使用扫描）。通过在LFSR的串行输出端改变带有位固定逻辑的伪随机位序列，生成检测随机模式抗故障的确定性测试立方体。用于合成位固定逻辑的过程允许以低硬件开销完成故障覆盖。此外，本方法允许使用小的LFSR来生成伪随机比特序列。由于LFSR中的线性相关性而未检测到的故障可以通过以额外的位固定逻辑为代价产生更多的确定性立方体来检测。

7. 发明申请

US20120173940A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20120173940A1
公开(公告)日：2012-07-05
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

8. 发明授权

US08161441B2 Robust scan synthesis for protecting soft errors 有权
标题翻译：用于保护软错误的强大的扫描合成
公开(公告)号：US08161441B2
公开(公告)日：2012-04-17
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

9. 发明授权

US07996741B2 Method and apparatus for low-pin-count scan compression 有权
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US07996741B2
公开(公告)日：2011-08-09
申请号：US12546060
申请日：2009-08-24
申请人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/28 , G06F11/00 , G06F9/455
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

10. 发明申请

US20110022908A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20110022908A1
公开(公告)日：2011-01-27
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

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