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1. 发明授权

US09389844B2 Solution for a computer system 有权
标题翻译：计算机系统的解决方案
公开(公告)号：US09389844B2
公开(公告)日：2016-07-12
申请号：US10963138
申请日：2004-10-12
申请人： Nicholas D. Butler , Christine M. Draper , John W. Sweitzer , Marcello Vitaletti
发明人： Nicholas D. Butler , Christine M. Draper , John W. Sweitzer , Marcello Vitaletti
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F8/61
摘要： An apparatus and a method provide a solution for a computer system. The apparatus may include a package containing or referencing a plurality of software components of the solution and containing a solution definition defining in logical terms the topology requirements of the solution. The plurality of software components may be packaged as installable units which comprise a descriptor providing requirements of a target hosting environment for the software component and the software component to be installed. The solution definition of the package may include target hosting environments of the software components of a solution being defined in terms of requirements each software component has on its own target hosting environment and requirements the solution imposes on the target hosting environments.
摘要翻译：一种装置和方法为计算机系统提供解决方案。该装置可以包括包含或引用解决方案的多个软件组件的包，并且包含以逻辑术语定义解决方案的拓扑要求的解决方案定义。多个软件组件可以被打包为可安装的单元，其包括提供用于软件组件和要安装的软件组件的目标托管环境的需求的描述符。软件包的解决方案定义可能包括解决方案的软件组件的目标托管环境，根据每个软件组件对其自己的目标托管环境的要求和解决方案对目标托管环境的要求进行定义。

2. 发明申请

US20120233295A1 Declarative Service Domain Federation 有权
标题翻译：声明服务域联合
公开(公告)号：US20120233295A1
公开(公告)日：2012-09-13
申请号：US13046008
申请日：2011-03-11
申请人： Daniel Bauer , Nicholas D. Butler , Han Chen , Kristijan Dragicevic , Luis Garces-Erice , Gidon Gershinsky , Minkyong Kim , Hui Lei , David Rushall , Marc-Thomas H. Schmidt , Konstantin Shagin , Hao Yang , Liangzhao Zeng
发明人： Daniel Bauer , Nicholas D. Butler , Han Chen , Kristijan Dragicevic , Luis Garces-Erice , Gidon Gershinsky , Minkyong Kim , Hui Lei , David Rushall , Marc-Thomas H. Schmidt , Konstantin Shagin , Hao Yang , Liangzhao Zeng
IPC分类号： G06F15/177
CPC分类号： H04L41/5003 , G06F9/5061 , H04L41/0806 , H04L41/5009 , H04L67/2838
摘要： A mechanism for declarative service domain federation uses a declarative approach to both the visibility aspect and the management aspect of service domain federation. Instead of manually exporting services, that is, selecting individual services from source domains to be visible in the target domain, using the present system, a federation architect uses a federation console to specify federation intent. The federation intent may include federation rule, query-based service group, and quality-of-service (QoS) policy. Based on the declared federation intent, a planning engine resolves the individual services based on the group query, generates the service visibility configuration, and creates the necessary service proxies and/or mediation objects to satisfy the goal. At runtime, a service monitor collects the performance metrics of federated services and dynamically adjusts the mediation/proxy configurations to maintain the QoS objectives specified by the federation architect.
摘要翻译：声明性服务域联合的机制对服务域联合的可见性方面和管理方面使用声明式方法。代替手动导出服务，即从源域中选择单个服务在目标域中可见，使用本系统，联合架构师使用联合控制台来指定联合意图。联盟意图可以包括联合规则，基于查询的服务组和服务质量（QoS）策略。基于声明的联盟意图，计划引擎基于组查询来解析各个服务，生成服务可见性配置，并创建必要的服务代理和/或中介对象以满足目标。在运行时，服务监视器收集联合服务的性能指标，并动态调整中介/代理配置，以维护联盟架构师指定的QoS目标。

3. 发明授权

US5280616A Logic circuit for task processing 失效
标题翻译：用于任务处理的逻辑电路
公开(公告)号：US5280616A
公开(公告)日：1994-01-18
申请号：US890330
申请日：1992-05-26
申请人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
发明人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/46 , G06F9/48 , G06F11/14 , G06F1/06 , G06F11/00
CPC分类号： G06F9/4881 , G06F9/30043 , G06F9/30141 , G06F9/3851 , G06F9/3861 , G06F9/461 , G06F11/14
摘要： In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.
摘要翻译：在具有时钟状态锁存器和组合逻辑的逻辑电路中，响应于状态锁存器的功能时钟来执行任务的功能处理，状态锁存器被附加地互连以形成可扫描的锁存器链，并且提供任务切换逻辑用于暂停任务通过中断状态锁存器的功能时钟来处理，并且在这种暂停期间扫描状态锁存器，使得可以从状态锁存器或定义任务状态的新内容中保存定义任务状态的状态锁存器的现有内容，状态锁定。本发明提供了一种用于在多处理环境中由逻辑电路执行的切换任务的有效手段。

4. 发明授权

US09389922B2 Declarative service domain federation 有权
标题翻译：声明式服务域联合
公开(公告)号：US09389922B2
公开(公告)日：2016-07-12
申请号：US13046008
申请日：2011-03-11
申请人： Daniel Bauer , Nicholas D. Butler , Han Chen , Kristijan Dragicevic , Luis Garces-Erice , Gidon Gershinsky , Minkyong Kim , Hui Lei , David Rushall , Marc-Thomas H. Schmidt , Konstantin Shagin , Hao Yang , Liangzhao Zeng
发明人： Daniel Bauer , Nicholas D. Butler , Han Chen , Kristijan Dragicevic , Luis Garces-Erice , Gidon Gershinsky , Minkyong Kim , Hui Lei , David Rushall , Marc-Thomas H. Schmidt , Konstantin Shagin , Hao Yang , Liangzhao Zeng
IPC分类号： G06F9/50
CPC分类号： H04L41/5003 , G06F9/5061 , H04L41/0806 , H04L41/5009 , H04L67/2838
摘要： A mechanism for declarative service domain federation uses a declarative approach to both the visibility aspect and the management aspect of service domain federation. Instead of manually exporting services, that is, selecting individual services from source domains to be visible in the target domain, using the present system, a federation architect uses a federation console to specify federation intent. The federation intent may include federation rule, query-based service group, and quality-of-service (QoS) policy. Based on the declared federation intent, a planning engine resolves the individual services based on the group query, generates the service visibility configuration, and creates the necessary service proxies and/or mediation objects to satisfy the goal. At runtime, a service monitor collects the performance metrics of federated services and dynamically adjusts the mediation/proxy configurations to maintain the QoS objectives specified by the federation architect.
摘要翻译：声明性服务域联合的机制对服务域联合的可见性方面和管理方面使用声明式方法。代替手动导出服务，即从源域中选择单个服务在目标域中可见，使用本系统，联合架构师使用联合控制台来指定联合意图。联盟意图可以包括联合规则，基于查询的服务组和服务质量（QoS）策略。基于声明的联盟意图，计划引擎基于组查询来解析各个服务，生成服务可见性配置，并创建必要的服务代理和/或中介对象以满足目标。在运行时，服务监视器收集联合服务的性能指标，并动态调整中介/代理配置，以维护联盟架构师指定的QoS目标。

5. 发明授权

US5450367A Split SAM with independent SAM access 失效
标题翻译：拆分SAM与独立的SAM访问
公开(公告)号：US5450367A
公开(公告)日：1995-09-12
申请号：US880118
申请日：1992-05-07
申请人： Nicholas D. Butler , Roderick M. P. West
发明人： Nicholas D. Butler , Roderick M. P. West
IPC分类号： G06F12/06 , G06F12/04 , G09G5/00 , G09G5/36 , G09G5/395 , G11C7/10 , G11C7/00
CPC分类号： G09G5/395 , G11C7/1075
摘要： Stored data for two different images superimposed on one another can be accessed simply and efficiently from the same VRAM. The SAM of the VRAM is divided into multiple-independent portions, each of which respond to its own independently controlled address counter. By loading the image data access into respective SAM portions, and switching data access between SAM portions at the SAM address rate, superimposed data of two different images can be displayed from the same VRAM.
摘要翻译：可以从相同的VRAM简单有效地访问彼此叠加的两个不同图像的存储数据。 VRAM的SAM被分成多个独立的部分，每个部分响应其自己的独立控制的地址计数器。通过将图像数据访问加载到各个SAM部分中，并且以SAM地址速率切换SAM部分之间的数据访问，可以从相同的VRAM显示两个不同图像的叠加数据。

6. 发明授权

US5157766A Boundary drawing and area filling logic for a display system 失效
标题翻译：用于显示系统的边界绘图和区域填充逻辑
公开(公告)号：US5157766A
公开(公告)日：1992-10-20
申请号：US484145
申请日：1990-02-23
申请人： Nicholas D. Butler , Adrian C. Gay
发明人： Nicholas D. Butler , Adrian C. Gay
IPC分类号： G09G5/36 , G06T11/40 , G09G5/393
CPC分类号： G09G5/393
摘要： A computer graphics system includes display logic (92) comprising a destination bit map (11) containing a plurality of image bits which map to a plurality of pixels for presenting an image, an auxiliary bit map (1) containing a plurality of area boundary bits representing pixels defining an area boundary line which encloses an area of the image, area filling logic (7) for operating upon those image bits enclosed by the area boundary line in order to fill the area with a particular pattern and color, characterized in that the display logic further comprises area boundary drawing logic (5) having line segmentation means to resolve the specified boundary line into a plurality of intersecting two pixel line segments which can, from that time forward, be operated upon separately to define the area boundary bits in accordance with conventional area boundary drawing rules.
摘要翻译：计算机图形系统包括显示逻辑（92），包括目的地位图（11），其包含映射到用于呈现图像的多个像素的多个图像位;辅助位图（1），其包含多个区域边界位表示限定包围图像区域的区域边界线的像素，区域填充逻辑（7），用于对由区域边界线包围的那些图像位进行操作，以便填充具有特定图案和颜色的区域，其特征在于，显示逻辑还包括区域边界绘制逻辑（5），其具有线分割装置，用于将指定的边界线分解为多个相交的两个像素线段，其可以从该时间向前分开操作以根据相应的区域边界位具有传统的区域划界规则。

7. 发明授权

US4996653A Line generation in a display system 失效
标题翻译：显示系统中的线生成
公开(公告)号：US4996653A
公开(公告)日：1991-02-26
申请号：US138241
申请日：1987-12-28
申请人： Nicholas D. Butler , Adrian C. Gay , Jack E. Bresenham
发明人： Nicholas D. Butler , Adrian C. Gay , Jack E. Bresenham
IPC分类号： G06F3/153 , G06T11/20 , G09G1/10 , G09G5/20 , G09G5/36
CPC分类号： G09G1/10 , G09G5/20
摘要： In a line generator and a method for determining the individual pixels to be plotted for a line to be drawn in a display system, coded representations of a plurality of lines are stored in a line definition table. The coded representation of each individual line is a string of data items representing the transitions between adjacent pixels to be plotted for drawing the individual line. Preferably, only coded representations of lines up to a predetermined size (i.e. the length of the line in the case of a straight line) are stored in the line definition table. Strings of data items for representing the pixels to be plotted for longer lines to be drawn are still calculated as in the prior art. In this case, control logic determines whether there are coded representations of a line to be drawn in the line definition table, or not, and passes control to appropriate processing logic for determining the pixels to be plotted. In a preferred embodiment, the string of data items forming the coded representation of a line to be drawn is a string of binary digits and the value of each bit in the string represents a transition in one of two directions. This provides a very compact representation of the line.

8. 发明授权

US09367358B2 Virtualizing a set of managers to form a composite manager in an autonomic system 有权
标题翻译：虚拟化一组管理器，以在自治系统中形成复合管理器
公开(公告)号：US09367358B2
公开(公告)日：2016-06-14
申请号：US11382104
申请日：2006-05-08
申请人： Kathryn H. Britton , Nicholas D. Butler , Peter J. Brittenham , Brent A. Miller
发明人： Kathryn H. Britton , Nicholas D. Butler , Peter J. Brittenham , Brent A. Miller
IPC分类号： G06F9/50 , G06F9/455 , G06Q10/06 , G06Q10/10
CPC分类号： G06F9/5061 , G06F9/455 , G06Q10/06 , G06Q10/10
摘要： A composite manager may include a set of managers virtualized as a single entity. The composite manager may also include at least one of a module to provide a single manager interface for the set of managers to manage at least one entity, and a module to provide a single manageability interface for the set of managers relative to any managing entity of the composite manager.
摘要翻译：复合管理器可以包括虚拟化为单个实体的一组管理器。复合管理器还可以包括模块中的至少一个以为该组管理器提供单个管理器接口以管理至少一个实体，以及模块，为该组管理者提供相对于任何管理实体的管理实体的单个可管理性接口复合经理。

9. 发明授权

US5157286A Conditional clocking of the second latch of a shift register ratch 失效
标题翻译：移位寄存器的第二个锁存器的条件时钟
公开(公告)号：US5157286A
公开(公告)日：1992-10-20
申请号：US484144
申请日：1990-02-23
申请人： Nicholas D. Butler , Roy B. Harrison
发明人： Nicholas D. Butler , Roy B. Harrison
IPC分类号： G01R31/28 , G01R31/3185 , G06F1/04 , G06F1/10 , G06F11/22 , G11C19/00
CPC分类号： G01R31/318558 , G01R31/318552 , G06F1/10 , G11C19/00
摘要： A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in response to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
摘要翻译：呈现包括多个寄存器30,39的逻辑电路; 每个寄存器30具有第一寄存器锁存器31,41，用于响应于第一时钟信号37将数据计时到寄存器30中;以及第二寄存器锁存器，用于响应于第二时钟信号38将数据输出寄存器;以及组合逻辑包括地址用于将数据寻址到寄存器的逻辑4和用于响应于地址逻辑禁止输入到寄存器的第一时钟信号的第一抑制逻辑33，其中逻辑电路还包括第二抑制逻辑34,35，用于禁止第二时钟信号输入该寄存器集中响应地址逻辑和第一个时钟信号。

10. 发明授权

US5081607A Arithmetic logic unit 失效
标题翻译：算术逻辑单元
公开(公告)号：US5081607A
公开(公告)日：1992-01-14
申请号：US483859
申请日：1990-02-23
申请人： Matthew D. Bates , Nicholas D. Butler , Adrian C. Gay , Jong H. Kim , Roderick M. West
发明人： Matthew D. Bates , Nicholas D. Butler , Adrian C. Gay , Jong H. Kim , Roderick M. West
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506 , G06T1/20
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.

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