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    • 3. 发明申请
    • Portable information terminal apparatus, voltage measurement apparatus, voltage measurement method and program thereof
    • 便携式信息终端装置,电压测量装置,电压测量方法及程序
    • US20070176592A1
    • 2007-08-02
    • US11442610
    • 2006-05-30
    • Kouhei HondaNaoki Kurihara
    • Kouhei HondaNaoki Kurihara
    • G01R11/32
    • G01R19/2503G06F1/28
    • The measurement unit measures a voltage by converting it from analog to digital and outputs a measurement value. The changeover unit, being connected to a battery and a reference voltage source generating a highly accurate fixed voltage, selects one of them and applies it to the measurement unit. The voltage value output unit makes the changeover unit select a fixed voltage generated by a predetermined voltage source, makes the measurement unit measure it as a reference voltage and generates calculation-use information for calculating a voltage value from a measurement result based on a measurement value of the fixed voltage and a voltage value of the reference voltage. The voltage value output unit, when making the changeover unit select a voltage of the battery and making the measurement unit measure it, uses the measurement value of it and the calculation-use information to calculate and output a voltage value of the battery.
    • 测量单元通过将其从模拟转换为数字测量电压并输出测量值。 连接到电池的转换单元和产生高精度固定电压的基准电压源选择其中之一并将其施加到测量单元。 电压值输出单元使切换单元选择由预定电压源产生的固定电压,使测量单元测量其作为参考电压,并且基于测量值产生用于从测量结果计算电压值的计算用信息 的固定电压和参考电压的电压值。 电压值输出单元在切换单元选择电池的电压并使测量单元测量时,使用其测量值和计算用途信息来计算并输出电池的电压值。
    • 4. 发明授权
    • Delay time control circuit
    • 延时控制电路
    • US06307403B1
    • 2001-10-23
    • US09461391
    • 1999-12-15
    • Naoki KuriharaJun Iida
    • Naoki KuriharaJun Iida
    • H03K513
    • H03K5/131H03K5/133
    • A delay time control circuit comprises a delay circuit composed of 2n series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, buffer circuits each connected to an output of each of the first and second inverters of the unit delay circuits of the delay circuit, 2n−1 first connection lines each connecting between outputs of adjacent ones of the buffer circuits connected to the second inverters and 2n−2 second connection lines each connecting between adjacent ones of the first connection lines. In response to an input signal input to the first inverter of first one of the unit delay circuit, an output signal delayed with respect to the input signal is obtained through one of the first connection lines and one of the second connection lines.
    • 延迟时间控制电路包括由2n个串联单元延迟电路构成的延迟电路,每个延迟电路包括一对串联连接的第一和第二反相器,其中n是等于或大于2的整数,每个连接到 延迟电路的单位延迟电路的第一和第二反相器的每一个的输出,连接到连接到第二反相器的相邻缓冲电路的输出之间的2n-1个第一连接线和连接到第二反相器的2n-2个第二连接线 在相邻的第一连接线之间。 响应于输入到单元延迟电路中的第一个的第一反相器的输入信号,通过第一连接线和第二连接线中的一个获得相对于输入信号延迟的输出信号。
    • 6. 发明申请
    • Sound Volume Control Circuit, Semiconductor Integrated Circuit And Sound Source Device
    • 音量控制电路,半导体集成电路和声源设备
    • US20070211910A1
    • 2007-09-13
    • US11547601
    • 2005-04-04
    • Naoki Kurihara
    • Naoki Kurihara
    • H03G3/00
    • H04R29/001H03G3/002
    • In a sound volume control circuit (100) shown in FIG. 2, an attenuation coefficient setting register (28) holds an attenuation coefficient “b”. When a stop instruction STOP becomes active, an output signal “a” from a first multiplexer (14), i.e., a processing object signal “in” is multiplied by the attenuation coefficient “b” by a multiplier (16), and the output signal “c” is outputted via a second multiplexer (18), a first flip-flop (20), and a third multiplexer (22). A multiplication master counter (38) holds the number of times the processing object signal “in” acquired by one sampling is multiplied by “b”. The multiplication master counter (38) counts up by using a timer (36). A multiplication temporary counter (32) loads the output signal from the multiplication master counter (38) at the assert of an acquisition timing signal “L”. The process from the first multiplexer (14) to the first flip-flop (20) is repeated by the number of times of the multiplication temporary counter (32).
    • 在图1所示的音量控制电路(100)中, 如图2所示,衰减系数设定寄存器(28)保持衰减系数“b”。 当停止指令STOP变为有效时,来自第一多路复用器(14)的输出信号“a”即处理对象信号“in”乘以衰减系数“b”乘以乘法器(16),输出 经由第二多路复用器(18),第一触发器(20)和第三多路复用器(22)输出信号“c”。 乘法主计数器(38)将通过一个采样获得的处理对象信号“in”的次数乘以“b”。 乘法主计数器(38)通过使用定时器(36)向上计数。 乘法临时计数器(32)在获取定时信号“L”的断言下加载来自乘法主计数器(38)的输出信号。 从第一多路复用器(14)到第一触发器(20)的处理重复乘法临时计数器(32)的次数。
    • 7. 发明授权
    • Delay circuit
    • 延时电路
    • US06333652B1
    • 2001-12-25
    • US09577013
    • 2000-05-24
    • Jun IidaYoshikazu IinumaNaoki KuriharaTakashi Nemoto
    • Jun IidaYoshikazu IinumaNaoki KuriharaTakashi Nemoto
    • H03L700
    • H03L7/0805H03L7/0891H03L7/0995H03L7/18
    • A delay circuit having a delay element circuit composed of a plurality of series-connected first circuit elements being connected to a common power supply line and having a delay time varying correspondingly to a voltage of the common power supply line, the delay element circuit being adapted to receive an input signal and output an output signal obtained by delaying the input signal, and a PLL circuit including an oscillator circuit composed of a plurality of series-connected second circuit elements, which are equivalent to the first circuit elements, respectively, are connected to the common power supply line. The PLL circuit is adapted to oscillate the oscillator circuit at a predetermined frequency locked to a reference clock frequency by comparing a phase of the reference clock signal with a phase of an output frequency of the oscillator circuit and controlling the voltage of the power supply line according to a result of the comparison.
    • 一种延迟电路,具有由多个串联连接的第一电路元件构成的延迟元件电路,所述延迟元件电路连接到公共电源线并且具有对应于所述公共电源线的电压的延迟时间变化,所述延迟元件电路适于 接收输入信号并输出​​通过延迟输入信号而获得的输出信号,并且分别包括与多个串联连接的第二电路元件组成的振荡器电路的PLL电路分别等效于第一电路元件 到公共电源线。 PLL电路适于通过将参考时钟信号的相位与振荡器电路的输出频率的相位进行比较并将电源线的电压进行比较来将振荡器电路以锁定到参考时钟频率的预定频率振荡, 比较的结果。