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1. 发明申请

US20150278025A1 CHECKPOINTS ASSOCIATED WITH AN OUT OF ORDER ARCHITECTURE 有权
标题翻译：与订单结构相关的检查点
公开(公告)号：US20150278025A1
公开(公告)日：2015-10-01
申请号：US14224233
申请日：2014-03-25
申请人： Dennis M. Khartikov , John H. Kelm , Naveen Neelakantam
发明人： Dennis M. Khartikov , John H. Kelm , Naveen Neelakantam
IPC分类号： G06F11/14 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction.
摘要翻译：描述了与处理设备的基于无序的架构相关联的检查点技术。其退出单元可以接收指令，并且执行关于指令是否与推测性错误相关联的标识。如果指令与推测性错误相关联，则可以执行第一操作以用第二检查点的状态值替换处理设备的第一检查点的状态值。如果该指令不与推测性错误相关联，则可以基于指令更新第二检查点状态。

2. 发明授权

US09569212B2 Instruction and logic for a memory ordering buffer 有权
标题翻译：存储器排序缓冲区的指令和逻辑
公开(公告)号：US09569212B2
公开(公告)日：2017-02-14
申请号：US14229007
申请日：2014-03-28
申请人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
发明人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30174 , G06F9/3808 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
摘要翻译：处理器包括具有向指令的原子区域内的指令分配别名硬件资源的逻辑分配器。原子区域包括重新排序的指令。该处理器还包括一个调度器，该调度器具有从用于执行的指令的原子区域分派指令的逻辑。此外，处理器包括具有逻辑的存储器执行单元，该逻辑使用来自包括重新排序的指令，接收窥探请求的指令的原子区域的指令来填充存储器执行单元，并且确定窥探请求是否匹配存储器执行单元内的元素的存储器地址数据，并且防止别名硬件资源重新分配给符合snoop请求的任何加载指令。

3. 发明申请

US20150277914A1 LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS 审中-公开
标题翻译：基于二进制翻译的处理器的锁定
公开(公告)号：US20150277914A1
公开(公告)日：2015-10-01
申请号：US14227014
申请日：2014-03-27
申请人： John H. Kelm , Naveen Neelakantam , Denis M. Khartikov
发明人： John H. Kelm , Naveen Neelakantam , Denis M. Khartikov
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/45516 , G06F9/4552
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for detection and exploitation of lock elision opportunities with binary translation based processors. The device may include a dynamic binary translation (DBT) module to translate a region of code from a first instruction set architecture (ISA) to translated code in a second ISA and to detect and elide a lock associated with a critical section of the region of code. The device may also include a processor to speculatively execute the translated code in the critical section. The device may further include a transactional support processor to detect a memory access conflict associated with the lock and/or critical section during the speculative execution, roll back the speculative execution in response to the detection, and commit the speculative execution in the absence of the detection.
摘要翻译：通常，本公开提供了用于基于二进制翻译的处理器来检测和利用锁定机会的系统，设备，方法和计算机可读介质。该设备可以包括动态二进制转换（DBT）模块，以将来自第一指令集体系结构（ISA）的代码区域转换为第二ISA中的转换代码，并且检测和删除与该区域的关键部分相关联的锁定码。该设备还可以包括在临界区域中推测性地执行转换的代码的处理器。该装置还可以包括事务支持处理器，用于在推测性执行期间检测与锁和/或关键部分相关联的存储器访问冲突，以响应于该检测来回滚推测性执行，并且在没有检测。

4. 发明申请

US20150277911A1 Instruction and Logic for a Logical Move in an Out-Of-Order Processor 有权
标题翻译：用于在乱序处理器中逻辑移动的指令和逻辑
公开(公告)号：US20150277911A1
公开(公告)日：2015-10-01
申请号：US14229179
申请日：2014-03-28
申请人： Denis M. Khartikov , Rupert Brauch , Raul Martinez , Naveen Neelakantam , Thang Vu
发明人： Denis M. Khartikov , Rupert Brauch , Raul Martinez , Naveen Neelakantam , Thang Vu
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3017 , G06F9/384 , G06F9/3855
摘要： A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.
摘要翻译：处理器包括具有用于接收逻辑移动指令的逻辑的分配单元。逻辑移动指令包括作为源参数的源逻辑寄存器和作为目的地参数的目的地逻辑寄存器。源逻辑寄存器被分配给源物理寄存器，目的地逻辑寄存器被分配给目的物理寄存器。分配单元包括将源逻辑寄存器的第一值分配给目的地逻辑寄存器并且在将第一值分配给目的地逻辑寄存器之前和之后维持目的物理寄存器的第二值的逻辑。

5. 发明申请

US20150378731A1 APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE 审中-公开
标题翻译：一种有效执行处理器管道的装置和方法
公开(公告)号：US20150378731A1
公开(公告)日：2015-12-31
申请号：US14319265
申请日：2014-06-30
申请人： PATRICK P. LAI , ETHAN SCHUCHMAN , DAVID KEPPEL , DENIS M. KHARTIKOV , POLYCHRONIS XEKALAKIS , JOSHUA B. FRYMAN , ALLAN D. KNIES , NAVEEN NEELAKANTAM , GREGOR STELLPFLUG , JOHN H. KELM , MIREM HYUSEINOVA , DEMOS PAVLOU , JAROSLAW TOPP
发明人： PATRICK P. LAI , ETHAN SCHUCHMAN , DAVID KEPPEL , DENIS M. KHARTIKOV , POLYCHRONIS XEKALAKIS , JOSHUA B. FRYMAN , ALLAN D. KNIES , NAVEEN NEELAKANTAM , GREGOR STELLPFLUG , JOHN H. KELM , MIREM HYUSEINOVA , DEMOS PAVLOU , JAROSLAW TOPP
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F15/76 , G06F9/30174 , G06F9/3824 , G06F9/3832 , G06F9/4552
摘要： Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
摘要翻译：描述了本发明的各种不同的实施例，包括：（1）用于在二进制翻译系统内智能分配线程的方法和装置; （2）由二进制翻译代码变形软件引导的数据缓存方式预测; （3）数据端的快速解释器硬件支持; （4）无序退休; （5）在原子处理器中解耦负载退休; （6）处理基于二进制翻译的处理器中的事务和原子存储器; 和（7）基于二进制翻译的按顺序处理器的推测内存管理。

6. 发明申请

US20140189659A1 HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYING CODE 有权
标题翻译：二进制翻译自修改代码和交叉修改代码的处理
公开(公告)号：US20140189659A1
公开(公告)日：2014-07-03
申请号：US13997694
申请日：2012-12-27
申请人： Nirajan L. Cooray , David Keppel , Naveen Kumar , Ori Lempel , Michael Neilly , Naveen Neelakantam , H. Peter Anvin , Sebastian Winkel
发明人： Nirajan L. Cooray , David Keppel , Naveen Kumar , Ori Lempel , Michael Neilly , Naveen Neelakantam , H. Peter Anvin , Sebastian Winkel
IPC分类号： G06F9/455
CPC分类号： G06F9/45525
摘要： A processor core includes a processor to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.
摘要翻译：处理器核心包括处理器，用于执行从存储在第一页中的第一指令转换的第一翻译指令。处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。其他实施例被描述为所要求保护的。

7. 发明申请

US20080052691A1 Communicating with and recovering state information from a dynamic translator 审中-公开
标题翻译：与动态翻译者沟通和恢复状态信息
公开(公告)号：US20080052691A1
公开(公告)日：2008-02-28
申请号：US11478965
申请日：2006-06-29
申请人： Naveen Neelakantam , Gregory M. Lueck , Christopher L. Elford , Suresh Srinivas , Robert S. Cohn
发明人： Naveen Neelakantam , Gregory M. Lueck , Christopher L. Elford , Suresh Srinivas , Robert S. Cohn
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F11/3612
摘要： A technique includes communicating a message to a dynamic translator in response to a change, which affects the validity of a translation that is performed by the dynamic translator.
摘要翻译：一种技术包括响应于影响由动态翻译器执行的翻译的有效性的变化而将消息传达给动态翻译器。

8. 发明申请

US20150277975A1 Instruction and Logic for a Memory Ordering Buffer 有权
标题翻译：内存订购缓冲区的指令和逻辑
公开(公告)号：US20150277975A1
公开(公告)日：2015-10-01
申请号：US14229007
申请日：2014-03-28
申请人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
发明人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
IPC分类号： G06F9/48 , G06F9/30 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30174 , G06F9/3808 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
摘要翻译：处理器包括具有向指令的原子区域内的指令分配别名硬件资源的逻辑的分配器。原子区域包括重新排序的指令。该处理器还包括一个调度器，该调度器具有从用于执行的指令的原子区域分派指令的逻辑。此外，处理器包括具有逻辑的存储器执行单元，该逻辑使用来自包括重新排序的指令，接收窥探请求的指令的原子区域的指令来填充存储器执行单元，并且确定窥探请求是否匹配存储器执行单元内的元素的存储器地址数据，并且防止别名硬件资源重新分配给符合snoop请求的任何加载指令。

9. 发明申请

US20140181388A1 Method And Apparatus To Implement Lazy Flush In A Virtually Tagged Cache Memory 有权
标题翻译：在几乎标记的高速缓冲存储器中实现懒惰冲洗的方法和装置
公开(公告)号：US20140181388A1
公开(公告)日：2014-06-26
申请号：US13724848
申请日：2012-12-21
申请人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
发明人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
IPC分类号： G11C7/10 , G06F12/08
CPC分类号： G11C7/1072 , G06F12/0804 , G06F12/0891 , G06F12/1036
摘要： A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.
摘要翻译：处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。高速缓冲存储器还包括多条高速缓存行。每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。其他实施例被描述为所要求保护的。

10. 发明申请

US20080244544A1 Using hardware checkpoints to support software based speculation 审中-公开
标题翻译：使用硬件检查点来支持基于软件的猜测
公开(公告)号：US20080244544A1
公开(公告)日：2008-10-02
申请号：US11729724
申请日：2007-03-29
申请人： Naveen Neelakantam , Craig Zilles , Uma Srinivasan , Suresh Srinivas , Ravi Rajwar , Konrad Lai
发明人： Naveen Neelakantam , Craig Zilles , Uma Srinivasan , Suresh Srinivas , Ravi Rajwar , Konrad Lai
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： Hardware checkpoints may be used to mark software-based speculation regions. An instruction may be provided at the beginning of a speculation region and at the end of the speculation region. If an exception occurs during the speculation region, a hardware rollback may be occurred. The hardware rollback rolls back to the instruction at the beginning of the speculation region. The hardware may take a checkpoint by taking a register snapshot and treating future memory updates as tentative. When the instruction marking the end of the speculation is reached, all the tentative memory updates are committed and the previously taken register snapshot is discarded.
摘要翻译：硬件检查点可用于标记基于软件的推测区域。可以在投机区域的开始处和投机区域的末尾提供指令。如果在推测区域发生异常，则可能会发生硬件回滚。硬件回滚回滚到投机区域开头的指令。硬件可以通过注册快照并将未来的内存更新视为暂时性来检查点。当达到臆测结束的指示时，所有暂时的内存更新被提交，并且先前注册的注册快照被丢弃。

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