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1. 发明申请

US20180308463A1 INSULATING SPHERES AND METHOD OF MANUFACTURING SAME 审中-公开
公开(公告)号：US20180308463A1
公开(公告)日：2018-10-25
申请号：US16024877
申请日：2018-07-01
申请人： Afzal Muhammad Chaudhry
发明人： Afzal Muhammad Chaudhry
IPC分类号： G10K11/162 , B32B3/20 , B32B13/08 , B32B13/04 , B32B7/12 , E04C2/288 , E04B1/90
CPC分类号： G10K11/162 , B28B19/0092 , B32B3/20 , B32B7/12 , B32B13/047 , B32B13/08 , B32B2250/03 , B32B2250/40 , B32B2264/0257 , B32B2307/102 , B32B2307/304 , B32B2607/00 , E04B1/803 , E04B1/90 , E04B2001/7691 , E04C2/2885 , Y02A30/242 , Y02B80/12 , Y10T428/131 , Y10T428/1317 , Y10T428/1372 , Y10T428/2982
摘要： The present invention is a thermal and acoustic insulating sphere that has an evacuated hollow interior. The spheres are constructed of insulating materials, and the inner and outer surfaces of each sphere have highly reflective coatings evenly applied to them. The coatings applied to the inner and outer surfaces reduce the transmission of heat by conduction, convection, and radiation. Additionally, the spheres provide superior acoustic insulation due to the inability of sound to travel through the interior vacuum. The spheres can be used to produce insulating materials, for example, by embedding or positioning them within or between other materials, to provide thermal and acoustic insulation.

2. 发明申请

US20060267071A1 Low-cost, low-voltage single-layer polycrystalline EEPROM memory cell integration into BiCMOS technology 有权
标题翻译：低成本，低电压单层多晶EEPROM存储单元集成到BiCMOS技术中
公开(公告)号：US20060267071A1
公开(公告)日：2006-11-30
申请号：US11136140
申请日：2005-05-24
申请人： Damian Carver , Muhammad Chaudhry
发明人： Damian Carver , Muhammad Chaudhry
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L21/8249 , H01L27/0623 , H01L27/11558 , H01L29/42324 , H01L29/66825
摘要： An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.
摘要翻译：具有浮动栅极的EEPROM存储晶体管。浮置栅极使用BiCMOS工艺形成，并且具有靠近隧道二极管窗口的第一沉降掺杂区域和靠近耦合电容器区域的第二沉降片掺杂区域。可选的第三沉降片区域可以形成在EEPROM存储晶体管的源极结附近。此外，可以在第一和第二沉降片掺杂区域之间形成浅沟槽隔离（STI）区域。

3. 发明申请

US20060244073A1 FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS 审中-公开
标题翻译：用SiGe源/漏区制造EEPROM单元
公开(公告)号：US20060244073A1
公开(公告)日：2006-11-02
申请号：US11426371
申请日：2006-06-26
申请人： Muhammad Chaudhry
发明人： Muhammad Chaudhry
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.
摘要翻译： EEPROM存储单元使用硅 - 锗/硅和发射极多晶硅膜来制造浅源极/漏极区域以增加相对于阱的击穿电压。源极/漏极区域被制造为深度约为100nm（0.1μm（mum）），击穿电压为大约14伏特或更高。双极工艺中的阱的典型击穿电压约为10伏。由于实现的击穿电压增加，可以在单个集成电路芯片上制造EEPROM存储单元以及双极器件，并制造在公共半导体制造线上。

4. 发明申请

US20060008960A1 Fabrication of an EEPROM cell with SiGe source/drain regions 失效
标题翻译：用SiGe源/漏区制造EEPROM单元
公开(公告)号：US20060008960A1
公开(公告)日：2006-01-12
申请号：US10887990
申请日：2004-07-09
申请人： Muhammad Chaudhry
发明人： Muhammad Chaudhry
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.
摘要翻译： EEPROM存储单元使用硅 - 锗/硅和发射极多晶硅膜来制造浅源极/漏极区域以增加相对于阱的击穿电压。源极/漏极区域被制造为深度约为100nm（0.1μm（mum）），击穿电压为大约14伏特或更高。双极工艺中的阱的典型击穿电压约为10伏。由于实现的击穿电压增加，可以在单个集成电路芯片上制造EEPROM存储单元以及双极器件，并制造在公共半导体制造线上。

5. 发明申请

US20110307755A1 STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODE 有权
标题翻译：结构化低密度奇偶校验（LDPC）代码
公开(公告)号：US20110307755A1
公开(公告)日：2011-12-15
申请号：US13156942
申请日：2011-06-09
申请人： Michael LIVSHITZ , Aleksandar PURKOVIC , Nina BURNS , Sergey SUKHOBOK , Muhammad CHAUDHRY
发明人： Michael LIVSHITZ , Aleksandar PURKOVIC , Nina BURNS , Sergey SUKHOBOK , Muhammad CHAUDHRY
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362 , H03M13/6368 , H03M13/6393 , H04L1/0057 , H04L1/0068
摘要： A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.
摘要翻译：一种使用具有置换矩阵，伪置换矩阵或零矩阵的结构化基本奇偶校验矩阵作为组成子矩阵来构造低密度奇偶校验（LDPC）码的方法; 并将结构化基本奇偶校验矩阵扩展成扩展奇偶校验矩阵。使用结构化基本奇偶校验矩阵H = [Hd | Hp]，Hd构造LDPC码的方法是数据部分，Hp是奇偶校验矩阵的奇偶校验部分; 结构化基本奇偶校验矩阵的奇偶校验部分使得当扩展时，扩展奇偶校验矩阵的奇偶校验部分的倒数是稀疏的; 并将结构化基本奇偶校验矩阵扩展成扩展奇偶校验矩阵。一种通过使用扩展的LDPC码对可变大小的数据进行编码的方法; 并应用缩短，穿刺。

6. 发明申请

US20070087550A1 LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL 审中-公开
标题翻译：低电压单层多晶硅EEPROM存储单元
公开(公告)号：US20070087550A1
公开(公告)日：2007-04-19
申请号：US11548512
申请日：2006-10-11
申请人： Muhammad Chaudhry , Damian Carver
发明人： Muhammad Chaudhry , Damian Carver
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The present invention is an electronic memory cell and a method for the cell's fabrication comprising a The first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
摘要翻译：本发明是一种用于单元制造的电子存储单元和方法，包括：第一晶体管，被配置为耦合到位线。第一晶体管在被激活时具有基本为零的电压降，并被配置为控制存储器单元的操作。第二晶体管被配置为作为存储晶体管工作并耦合到第一晶体管。第二晶体管被进一步配置为可以以等于位线上的电压的电压来编程。

7. 发明申请

US20150225945A1 Heat and Sound Insulation Ball (HASIB) 审中-公开
标题翻译：隔热球（HASIB）
公开(公告)号：US20150225945A1
公开(公告)日：2015-08-13
申请号：US14176142
申请日：2014-02-09
申请人： Afzal Muhammad Chaudhry
发明人： Afzal Muhammad Chaudhry
IPC分类号： E04B1/88 , E04F13/075
CPC分类号： E04B1/90 , E04B1/803 , E04B2001/742 , E04B2001/7691 , Y02A30/242 , Y02B80/12 , Y10T428/131 , Y10T428/1317 , Y10T428/1372 , Y10T428/2982
摘要： Heat and Sound Insulation Ball (HASIB) is a hollow ball which has vacuum inside and is made of insulating materials like fiber-reinforced-plastic and glass. The inner and the outer surfaces of HASIB have non-conducting highly reflective coatings. HASIB is a much better heat insulator and its use can reduce the transmission of heat by conduction, convection and radiation. The use of HASIB for heat insulation can save energy and bring down the cost of heating in winter and cooling in summer. HASIB is also a better sound insulator since sound cannot travel through the vacuum inside it. HASIB can be used in the form of HASIB-wrap which can be made by gluing them between two sheets of plastic. HASIBs can also be embedded in the drywall used for the construction of houses to make the drywall a much better heat and sound insulator.
摘要翻译：隔热球（HASIB）是一种空心球，内部具有真空，由绝缘材料制成，如纤维增强塑料和玻璃。 HASIB的内表面和外表面具有非导电高反射涂层。 HASIB是一种更好的隔热材料，其使用可以通过传导，对流和辐射来减少热量的传播。使用HASIB进行隔热可以节约能源，降低冬季供暖成本，夏季降温。由于声音不能穿过其内部的真空，HASIB也是更好的隔音材料。 HASIB可以以HASIB包装的形式使用，其可以通过将它们粘合在两片塑料之间来制造。 HASIB也可以嵌入在用于建造房屋的干墙中，使干墙更好地散热和隔音。

8. 发明申请

US20130013983A1 STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODE 审中-公开
标题翻译：结构化低密度奇偶校验（LDPC）代码
公开(公告)号：US20130013983A1
公开(公告)日：2013-01-10
申请号：US13619420
申请日：2012-09-14
申请人： Michael Livshitz , Aleksandar Purkovic , Nina Burns , Sergey Sukhobok , Muhammad Chaudhry
发明人： Michael Livshitz , Aleksandar Purkovic , Nina Burns , Sergey Sukhobok , Muhammad Chaudhry
IPC分类号： H03M13/05
CPC分类号： H03M13/1111 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362 , H03M13/6368 , H03M13/6393 , H04L1/0057 , H04L1/0068
摘要： Example methods are disclosed for encoding variable sized data using a low-density parity-check (LDPC) code, and transporting the encoded variable sized data in modulated symbols. Example methods involve calculating a minimum number of modulated symbols capable of transmitting a data packet; selecting a codeword size suitable for transmitting the data packet; calculating a number of shortening Nshortened bits; and calculating a number of puncturing Npunctured bits, to thereby produce a shortened and punctured expanded parity check matrix for transmitting the data packet.
摘要翻译：公开了用于使用低密度奇偶校验（LDPC）码对可变大小的数据进行编码，以及以调制符号传输编码的可变大小数据的示例方法。示例性方法包括计算能够发送数据分组的调制符号的最小数量; 选择适于发送所述数据分组的码字大小; 计算一些缩短Nshortened位; 以及计算穿孔Npunctured比特的数量，从而产生用于发送数据分组的缩小和打孔的扩展奇偶校验矩阵。

9. 发明申请

US20100211847A1 STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODE 失效
标题翻译：结构化低密度奇偶校验（LDPC）代码
公开(公告)号：US20100211847A1
公开(公告)日：2010-08-19
申请号：US12704850
申请日：2010-02-12
申请人： MICHAEL LIVSHITZ , ALEKSANDAR PURKOVIC , NINA BURNS , SERGEY SUKHOBOK , MUHAMMAD CHAUDHRY
发明人： MICHAEL LIVSHITZ , ALEKSANDAR PURKOVIC , NINA BURNS , SERGEY SUKHOBOK , MUHAMMAD CHAUDHRY
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362 , H03M13/6368 , H03M13/6393 , H04L1/0057 , H04L1/0068
摘要： A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.
摘要翻译：一种使用具有置换矩阵，伪置换矩阵或零矩阵的结构化基本奇偶校验矩阵作为组成子矩阵来构造低密度奇偶校验（LDPC）码的方法; 并将结构化基本奇偶校验矩阵扩展成扩展奇偶校验矩阵。使用结构化基本奇偶校验矩阵H = [Hd | Hp]，Hd构造LDPC码的方法是数据部分，Hp是奇偶校验矩阵的奇偶校验部分; 结构化基本奇偶校验矩阵的奇偶校验部分使得当扩展时，扩展奇偶校验矩阵的奇偶校验部分的倒数是稀疏的; 并将结构化基本奇偶校验矩阵扩展成扩展奇偶校验矩阵。一种通过使用扩展的LDPC码对可变大小的数据进行编码的方法; 并应用缩短，穿刺。

10. 发明申请

US20090259915A1 Structured low-density parity-check (ldpc) code 有权
标题翻译：结构化低密度奇偶校验（ldpc）代码
公开(公告)号：US20090259915A1
公开(公告)日：2009-10-15
申请号：US11665171
申请日：2005-10-12
申请人： Michael Livshitz , Aleksandar Purkovic , Nina Burns , Sergey Sukhobok , Muhammad Chaudhry
发明人： Michael Livshitz , Aleksandar Purkovic , Nina Burns , Sergey Sukhobok , Muhammad Chaudhry
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362 , H03M13/6368 , H03M13/6393 , H04L1/0057 , H04L1/0068
摘要： The invention introduces an apparatus, method and system that allow coding matrices to be expanded to accommodate various information packet sizes and support for various code rates; additionally the invention defines a number of coding matrices particularly suited to the methodology. The invention enables high throughput implementations, allows achieving low latency, and offers other numerous implementation benefits. At the same time, the new parity part of the matrix preserves the simple (recursive) encoding feature.
摘要翻译：本发明引入了允许扩展编码矩阵以适应各种信息分组大小并支持各种码率的装置，方法和系统; 此外，本发明定义了特别适合该方法的多个编码矩阵。本发明实现了高吞吐量实现，允许实现低延迟，并且提供了其它许多实现益处。同时，矩阵的新的奇偶校验部分保留简单（递归）编码特征。

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