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1. 发明授权

US08796805B2 Multiple metal film stack in BSI chips 有权
标题翻译： BSI芯片中的多个金属膜堆叠
公开(公告)号：US08796805B2
公开(公告)日：2014-08-05
申请号：US13604380
申请日：2012-09-05
申请人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
发明人： Shyh-Fann Ting , Jiech-Fun Lu , Ming-I Wang , Yeur-Luen Tu , Ching-Chun Wang
IPC分类号： H01L31/00 , H01L21/00 , H01L27/146 , H01L21/768
CPC分类号： H01L27/1464 , H01L21/76838 , H01L27/14623 , H01L27/14687
摘要： A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
摘要翻译：一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。在第一导电层上形成第二导电层并与第一导电层接触。执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。执行第二图案化步骤以去除第一导电层的第一部分的一部分。在第二图案化步骤之后，第一导电层的第二和第三部分保留。

2. 发明授权

US08710601B2 MEMS structure and method for making the same 有权
标题翻译： MEMS结构及其制作方法
公开(公告)号：US08710601B2
公开(公告)日：2014-04-29
申请号：US12621526
申请日：2009-11-19
申请人： Chien-Hsin Huang , Bang-Chiang Lan , Ming-I Wang , Hui-Min Wu , Tzung-I Su , Chao-An Su , Tzung-Han Tan , Min Chen , Meng-Jia Lin
发明人： Chien-Hsin Huang , Bang-Chiang Lan , Ming-I Wang , Hui-Min Wu , Tzung-I Su , Chao-An Su , Tzung-Han Tan , Min Chen , Meng-Jia Lin
IPC分类号： H01L29/84
CPC分类号： H04R19/005 , B81B3/0072 , B81B2201/0221 , B81B2201/0257 , B81B2203/0127 , H01L29/84
摘要： A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.
摘要翻译：公开了一种微机电系统（MEMS）结构。 MEMS结构包括背板电极和3D隔膜电极。 3D隔膜电极具有复合结构，使得电介质设置在两个金属层之间。 3D隔膜电极与背板电极相邻，以形成可变电容器。

3. 发明授权

US08587078B2 Integrated circuit and fabricating method thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08587078B2
公开(公告)日：2013-11-19
申请号：US12754610
申请日：2010-04-06
申请人： Chien-Hsin Huang , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
发明人： Chien-Hsin Huang , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： H01L27/0617 , B81B2201/0257 , B81B2207/015 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , B81C2203/0771
摘要： A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
摘要翻译：提供了集成电路的制造方法。在集成电路的互连结构的制造过程中，在互连结构的两个相邻电介质层之间形成微机电系统（MENS）隔膜。形成MENS隔膜的方法包括以下步骤。首先，在任何电介质层内形成多个第一开口以暴露互连结构的相应的导电材料。其次，在电介质层上形成底部绝缘层并填充到第一开口中。第三，去除位于第一开口中的底部绝缘层的部分，以形成用于暴露相应导电材料的至少第一沟槽。然后，第一电极层和顶部绝缘层依次形成在底部绝缘层上，第一电极层被填充到第一沟槽中并与导电材料电连接。

4. 发明授权

US08460960B2 Method for fabricating integrated circuit 有权
标题翻译：集成电路制造方法
公开(公告)号：US08460960B2
公开(公告)日：2013-06-11
申请号：US13186607
申请日：2011-07-20
申请人： Meng-Jia Lin , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
发明人： Meng-Jia Lin , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/31144 , B81C1/00246 , B81C2203/0714 , H01L27/0617
摘要： A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.
摘要翻译：提供一种用于制造集成电路的方法。首先，在导电基板的MEMS区域上形成包括多个第一电介质层和交替堆叠的多个第一导电图案的第一互连结构。接下来，在第一互连结构上形成中间层并覆盖第一导电图案。接下来，在中间层上形成对应于第一导电图案的多晶硅掩模层，并暴露介质层的一部分。接下来，去除由多晶硅掩模层暴露的层的部分和与其对应的第一介电层的一部分，以形成多个开口。然后，去除MEMS区域中的导电衬底的一部分。

5. 发明申请

US20130023081A1 METHOD FOR FABRICATING INTEGRATED CIRCUIT 有权
标题翻译：制造集成电路的方法
公开(公告)号：US20130023081A1
公开(公告)日：2013-01-24
申请号：US13186607
申请日：2011-07-20
申请人： Meng-Jia LIN , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
发明人： Meng-Jia LIN , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , B81C1/00246 , B81C2203/0714 , H01L27/0617
摘要： A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.
摘要翻译：提供一种用于制造集成电路的方法。首先，在导电基板的MEMS区域上形成包括多个第一电介质层和交替堆叠的多个第一导电图案的第一互连结构。接下来，在第一互连结构上形成中间层并覆盖第一导电图案。接下来，在中间层上形成对应于第一导电图案的多晶硅掩模层，并暴露介质层的一部分。接下来，去除由多晶硅掩模层暴露的层的部分和与其对应的第一介电层的一部分，以形成多个开口。然后，去除MEMS区域中的导电衬底的一部分。

6. 发明申请

US20120205827A1 METHOD OF FABRICATING CONTIGUOUS MICROLENS ARRAY 有权
标题翻译：制作连续微阵列的方法
公开(公告)号：US20120205827A1
公开(公告)日：2012-08-16
申请号：US13457776
申请日：2012-04-27
申请人： Yu-Tsung Lin , Hsin-Ping Wu , Hung-Chao Kao , Ming-I Wang
发明人： Yu-Tsung Lin , Hsin-Ping Wu , Hung-Chao Kao , Ming-I Wang
IPC分类号： G02B1/12 , B29D11/00
CPC分类号： B29D11/00365 , G02B3/0018 , G02B3/0056 , G02B5/201 , G03F7/40
摘要： A method of fabricating a contiguous microlens array is disclosed. First, an array of photoresist patterns is formed, wherein each photoresist pattern has a substantially circular or polygonal shape in a top view and neighboring photoresist patterns are connected with each other or close to each other. Then a reflow step is performed to heat the photoresist patterns thereby rounding a surface of each photoresist pattern and connecting the neighboring photoresist patterns that are close to each other. Finally, a fixing step is performed to fix a shape of each photoresist pattern. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto.
摘要翻译：公开了制造连续微透镜阵列的方法。首先，形成光致抗蚀剂图案的阵列，其中每个光致抗蚀剂图案在顶视图中具有大致圆形或多边形形状，并且相邻的光致抗蚀剂图案彼此连接或彼此靠近。然后进行回流步骤以加热光致抗蚀剂图案，从而使每个光致抗蚀剂图案的表面四舍五入并且连接彼此靠近的相邻光致抗蚀剂图案。最后，执行定影步骤以固定每种光致抗蚀剂图案的形状。微透镜阵列中的微透镜的曲面的形状根据其在阵列中的位置和入射到其中的光的入射角度而被选择性地调节。

7. 发明授权

US08139907B2 Optoelectronic device and method of forming the same 有权
标题翻译：光电器件及其形成方法
公开(公告)号：US08139907B2
公开(公告)日：2012-03-20
申请号：US12648861
申请日：2009-12-29
申请人： Tzung-I Su , Ming-I Wang , Bang-Chiang Lan , Te-Kan Liao , Chao-An Su , Chien-Hsin Huang , Hui-Min Wu , Tzung-Han Tan , Min Chen , Meng-Jia Lin
发明人： Tzung-I Su , Ming-I Wang , Bang-Chiang Lan , Te-Kan Liao , Chao-An Su , Chien-Hsin Huang , Hui-Min Wu , Tzung-Han Tan , Min Chen , Meng-Jia Lin
IPC分类号： G02B6/12
CPC分类号： G02B6/12004 , G02B2006/12061
摘要： An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.
摘要翻译：提供了包括基板，半舟形材料层，深沟槽隔离结构和光波导的光电子器件。衬底具有第一区域。半船形材料层设置在第一区域内的基板内。半舟状材料层的折射率低于基板的折射率。半舟状材料层的上表面与基板的表面共面。深沟槽隔离结构设置在第一区域内的基板中，并且位于半舟形材料层的弓形部分的一侧。光波导路设置在第一区域内的基板上。光波导与深沟槽隔离结构的一部分和半舟形材料层的至少一部分重叠。

8. 发明申请

US20110241137A1 Integrated Circuit and Fabricating Method thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20110241137A1
公开(公告)日：2011-10-06
申请号：US12754610
申请日：2010-04-06
申请人： Chien-Hsin HUANG , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
发明人： Chien-Hsin HUANG , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： H01L27/0617 , B81B2201/0257 , B81B2207/015 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , B81C2203/0771
摘要： A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
摘要翻译：提供了集成电路的制造方法。在集成电路的互连结构的制造过程中，在互连结构的两个相邻电介质层之间形成微机电系统（MENS）隔膜。形成MENS隔膜的方法包括以下步骤。首先，在任何电介质层内形成多个第一开口以暴露互连结构的相应的导电材料。其次，在电介质层上形成底部绝缘层并填充到第一开口中。第三，去除位于第一开口中的底部绝缘层的部分，以形成用于暴露相应导电材料的至少第一沟槽。然后，第一电极层和顶部绝缘层依次形成在底部绝缘层上，第一电极层被填充到第一沟槽中并与导电材料电连接。

9. 发明申请

US20110158581A1 OPTOELECTRONIC DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：光电装置及其形成方法
公开(公告)号：US20110158581A1
公开(公告)日：2011-06-30
申请号：US12648861
申请日：2009-12-29
申请人： Tzung-I Su , Ming-I Wang , Bang-Chiang Lan , Te-Kan Liao , Chao-An Su , Chien-Hsin Huang , Hui-Min Wu , Tzung-Han Tan , Min Chen , Meng-Jia Lin
发明人： Tzung-I Su , Ming-I Wang , Bang-Chiang Lan , Te-Kan Liao , Chao-An Su , Chien-Hsin Huang , Hui-Min Wu , Tzung-Han Tan , Min Chen , Meng-Jia Lin
IPC分类号： G02B6/12 , H01L21/30
CPC分类号： G02B6/12004 , G02B2006/12061
摘要： An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer.
摘要翻译：提供了包括基板，半舟形材料层，深沟槽隔离结构和光波导的光电子器件。衬底具有第一区域。半船形材料层设置在第一区域内的基板内。半舟状材料层的折射率低于基板的折射率。半舟状材料层的上表面与基板的表面共面。深沟槽隔离结构设置在第一区域内的基板中，并且位于半舟形材料层的弓形部分的一侧。光波导路设置在第一区域内的基板上。光波导与深沟槽隔离结构的一部分和半舟形材料层的至少一部分重叠。

10. 发明申请

US20080217667A1 IMAGE SENSING DEVICE 审中-公开
标题翻译：图像传感装置
公开(公告)号：US20080217667A1
公开(公告)日：2008-09-11
申请号：US12124178
申请日：2008-05-21
申请人： Ming-I Wang
发明人： Ming-I Wang
IPC分类号： H01L31/00
CPC分类号： H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14685
摘要： An image sensing device includes a substrate with a photo sensing and a transistor region, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the substrate within the photo sensing region. The transistor is on the substrate in the transistor region. The dielectric layer is on the substrate. Except the photo sensing region, the metal interconnect and the metal conductive line are respectively located in and on the dielectric layer. The conformal passivation layer is on the dielectric layer and covers the metal conductive line. The color filter is on the conformal passivation layer in the photo sensing region and the bottom thereof is lower than the bottom of the metal conductive line. The lens planar layer and the microlens are sequentially on precedent structure.
摘要翻译：图像感测装置包括具有感光和晶体管区域的基板，光电二极管，晶体管，电介质层，金属互连，金属导电线，共形钝化层，滤色器，透镜平面层，和微透镜。光电二极管位于光感测区域内的衬底中。晶体管在晶体管区域的衬底上。电介质层在衬底上。除了感光区域之外，金属互连和金属导电线分别位于电介质层中和介质层上。保形钝化层位于电介质层上并覆盖金属导电线。滤色器位于感光区域中的保形钝化层上，其底部低于金属导电线的底部。透镜平面层和微透镜依次是先验结构。

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