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1. 发明授权

US08742498B2 High voltage semiconductor device and fabricating method thereof 有权
标题翻译：高压半导体器件及其制造方法
公开(公告)号：US08742498B2
公开(公告)日：2014-06-03
申请号：US13288072
申请日：2011-11-03
申请人： Fu-Chun Chien , Ching-Wei Teng , Nien-Chung Li , Chih-Chung Wang , Te-Yuan Wu , Li-Che Chen , Chih-Chun Pu , Yu-Ting Yeh , Kuan-Wen Lu
发明人： Fu-Chun Chien , Ching-Wei Teng , Nien-Chung Li , Chih-Chung Wang , Te-Yuan Wu , Li-Che Chen , Chih-Chun Pu , Yu-Ting Yeh , Kuan-Wen Lu
IPC分类号： H01L29/66 , H01L21/70
CPC分类号： H01L21/823481 , H01L21/823418 , H01L21/823493 , H01L27/088
摘要： A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.
摘要翻译：提供一种制造高电压半导体器件的方法。首先，提供衬底，其中衬底具有第一有源区和第二有源区。然后，进行第一离子注入工艺以通过第一掩模层掺杂衬底，从而在第一有源区的两端和第二有源区的周边形成第一极性掺杂区。在去除第一掩模层之后，执行第二离子注入工艺以通过第二掩模层掺杂衬底，从而在第二有源区的两端和第一有源区的周边形成第二极性掺杂区。在去除第二掩模层之后，分别在第一有源区和第二有源区的中间段上形成第一栅极导体结构和第二栅极导体结构。

2. 发明申请

US20130312246A1 METHOD FOR SUPPORTING SEMICONDUCTOR WAFER AND WAFER SUPPORTING ASSEMBLY 有权
标题翻译：支持半导体波形和波长支撑组件的方法
公开(公告)号：US20130312246A1
公开(公告)日：2013-11-28
申请号：US13479253
申请日：2012-05-23
申请人： Chang-Sheng Hsu , Li-Che Chen , Kuo-Yuh Yang , Chia-Wen Lien , Yan-Da Chen
发明人： Chang-Sheng Hsu , Li-Che Chen , Kuo-Yuh Yang , Chia-Wen Lien , Yan-Da Chen
IPC分类号： B23Q7/00 , B25B11/00
CPC分类号： B25B11/005 , B23Q3/1543
摘要： A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.
摘要翻译：一种用于支撑半导体晶片的方法包括：向可磁化环提供器件晶片，向器件晶片提供可磁化载体，以及使可磁化环和可磁化载体磁化，形成具有磁化环和磁化载体的磁化夹具。磁化夹具将设备晶片固定在其间。

3. 发明授权

US08587078B2 Integrated circuit and fabricating method thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08587078B2
公开(公告)日：2013-11-19
申请号：US12754610
申请日：2010-04-06
申请人： Chien-Hsin Huang , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
发明人： Chien-Hsin Huang , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： H01L27/0617 , B81B2201/0257 , B81B2207/015 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , B81C2203/0771
摘要： A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
摘要翻译：提供了集成电路的制造方法。在集成电路的互连结构的制造过程中，在互连结构的两个相邻电介质层之间形成微机电系统（MENS）隔膜。形成MENS隔膜的方法包括以下步骤。首先，在任何电介质层内形成多个第一开口以暴露互连结构的相应的导电材料。其次，在电介质层上形成底部绝缘层并填充到第一开口中。第三，去除位于第一开口中的底部绝缘层的部分，以形成用于暴露相应导电材料的至少第一沟槽。然后，第一电极层和顶部绝缘层依次形成在底部绝缘层上，第一电极层被填充到第一沟槽中并与导电材料电连接。

4. 发明申请

US20110241137A1 Integrated Circuit and Fabricating Method thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20110241137A1
公开(公告)日：2011-10-06
申请号：US12754610
申请日：2010-04-06
申请人： Chien-Hsin HUANG , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
发明人： Chien-Hsin HUANG , Li-Che Chen , Ming-I Wang , Bang-Chiang Lan , Tzung-Han Tan , Hui-Min Wu , Tzung-I Su
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： H01L27/0617 , B81B2201/0257 , B81B2207/015 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , B81C2203/0771
摘要： A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
摘要翻译：提供了集成电路的制造方法。在集成电路的互连结构的制造过程中，在互连结构的两个相邻电介质层之间形成微机电系统（MENS）隔膜。形成MENS隔膜的方法包括以下步骤。首先，在任何电介质层内形成多个第一开口以暴露互连结构的相应的导电材料。其次，在电介质层上形成底部绝缘层并填充到第一开口中。第三，去除位于第一开口中的底部绝缘层的部分，以形成用于暴露相应导电材料的至少第一沟槽。然后，第一电极层和顶部绝缘层依次形成在底部绝缘层上，第一电极层被填充到第一沟槽中并与导电材料电连接。

5. 发明申请

US20100067728A1 MICROELECTROMECHANICAL SYSTEM MICROPHONE STRUCTURE AND MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE STRUCTURE 有权
标题翻译：微电子系统麦克风结构与微电子系统麦克风包装结构
公开(公告)号：US20100067728A1
公开(公告)日：2010-03-18
申请号：US12211650
申请日：2008-09-16
申请人： Li-Che Chen
发明人： Li-Che Chen
IPC分类号： H04R9/08
CPC分类号： H04R1/406 , H04R19/005 , H04R19/04 , H04R31/00
摘要： A microelectromechanical system microphone structure including a substrate, a first device and at least one second device is provided. The first device is disposed on the substrate and including a first upper electrode and a first lower electrode disposed between the first upper electrode and the substrate. The second device is disposed on the substrate, surrounding the first device and including a second upper electrode and a second lower electrode disposed between the second upper electrode and the substrate. The second upper electrode includes a plurality of first conductive layers and first plugs. The first conductive layers are arranged in steps, and the first plug is disposed between the adjacent first conductive layers. The second lower electrode includes a plurality of second conductive layers and a plurality of second plugs. The second conductive layers are arranged in steps, and the second plug is disposed between the adjacent second conductive layers.
摘要翻译：提供包括基板，第一装置和至少一个第二装置的微机电系统麦克风结构。第一器件设置在衬底上，并且包括设置在第一上电极和衬底之间的第一上电极和第一下电极。第二装置设置在基板上，围绕第一装置并且包括设置在第二上电极和基板之间的第二上电极和第二下电极。第二上电极包括多个第一导电层和第一插塞。第一导电层被分阶段布置，并且第一插头设置在相邻的第一导电层之间。第二下电极包括多个第二导电层和多个第二插塞。第二导电层被分阶段地布置，并且第二插头设置在相邻的第二导电层之间。

6. 发明授权

US08546739B2 Manufacturing method of wafer level chip scale package of image-sensing module 有权
标题翻译：晶片级芯片尺寸图像感应模块封装的制造方法
公开(公告)号：US08546739B2
公开(公告)日：2013-10-01
申请号：US12541153
申请日：2009-08-13
申请人： Min-Chih Hsuan , Tsung-Hsi Ko , Li-Che Chen
发明人： Min-Chih Hsuan , Tsung-Hsi Ko , Li-Che Chen
IPC分类号： H01J3/14 , H01J5/16
CPC分类号： H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14685 , H01L2224/05001 , H01L2224/05023 , H01L2224/13 , H01L2224/13025 , H01L2924/00014 , H04N5/2254 , H04N5/2257 , H01L2224/05599 , H01L2224/05099
摘要： A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips.
摘要翻译：提供了一种图像感测模块的晶片级芯片级封装的制造方法。该方法包括提供具有多个管芯区域的晶片，并且在每个管芯区域中在晶片的表面上形成多个感测单元。在感测单元上形成多个透镜单元，其中每个透镜单元包括一体形成的透镜和边缘壁。遮光膜也形成在至少一个透镜单元的至少一个边缘壁的表面上。然后在晶片上进行切割处理以形成多个图像传感器芯片。

7. 发明申请

US20120193735A1 MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE STRUCTURE 有权
标题翻译：微电子系统麦克风包装结构
公开(公告)号：US20120193735A1
公开(公告)日：2012-08-02
申请号：US13446651
申请日：2012-04-13
申请人： Li-Che CHEN
发明人： Li-Che CHEN
IPC分类号： H01L29/84
CPC分类号： H04R1/406 , H04R19/005 , H04R19/04 , H04R31/00
摘要： A microelectromechanical system microphone package structure includes a base plate and a plurality of chips is provided. The plurality of chips are disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are not parallel to each other.
摘要翻译：微机电系统麦克风封装结构包括基板，并提供多个芯片。多个芯片设置在基板上，其中每个芯片的有源区域设置有微机电系统麦克风结构，每个有源区域包括法线，并且芯片的法线不平行于彼此。

8. 发明授权

US07659501B2 Image-sensing module of image capture apparatus and manufacturing method thereof 有权
标题翻译：图像捕获装置的图像感测模块及其制造方法
公开(公告)号：US07659501B2
公开(公告)日：2010-02-09
申请号：US11693743
申请日：2007-03-30
申请人： Min-Chih Hsuan , Tsung-Hsi Ko , Li-Che Chen
发明人： Min-Chih Hsuan , Tsung-Hsi Ko , Li-Che Chen
IPC分类号： H01J3/14 , H01J5/16
CPC分类号： H04N5/2254 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14685 , H01L2924/0002 , H04N5/2257 , H01L2924/00
摘要： An image-sensing module is provided. The image-sensing module includes a substrate, a plurality of image-sensing units, a plurality of micro lenses and a focusing unit. The image-sensing units are disposed on the substrate and the micro lenses are respectively disposed on one of the image-sensing units. The focusing unit is disposed on the substrate and covers the micro lenses. A top surface of the focusing unit is a curved surface. Furthermore, a method of manufacturing the image-sensing module and an image capture apparatus are provided.
摘要翻译：提供图像感测模块。图像感测模块包括基板，多个图像感测单元，多个微透镜和聚焦单元。图像感测单元设置在基板上，微透镜分别设置在一个图像感测单元上。聚焦单元设置在基板上并覆盖微透镜。聚焦单元的顶表面是曲面。此外，提供了制造图像感测模块和图像捕获装置的方法。

9. 发明授权

US07368785B2 MOS transistor device structure combining Si-trench and field plate structures for high voltage device 有权
标题翻译： MOS晶体管器件结构组合了Si沟槽和场板结构的高压器件
公开(公告)号：US07368785B2
公开(公告)日：2008-05-06
申请号：US11420006
申请日：2006-05-24
申请人： Li-Che Chen , Chih-Chong Wang
发明人： Li-Che Chen , Chih-Chong Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0878 , H01L29/407 , H01L29/42368 , H01L29/66681 , H01L29/7823
摘要： A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.
摘要翻译：公开了一种高电压用金属氧化物半导体晶体管器件（HV MOS）及其制造方法。 HV MOS晶体管器件包括具有与多个场板结合的凹陷下表面的场氧化物区域，以延长用于干扰横向电场的路径，因此晶体管器件具有相对较小的尺寸。

10. 发明申请

US20130113048A1 HIGH VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：高电压半导体器件及其制造方法
公开(公告)号：US20130113048A1
公开(公告)日：2013-05-09
申请号：US13288072
申请日：2011-11-03
申请人： Fu-Chun CHIEN , Ching-Wei Teng , Nien-Chung Li , Chih-Chung Wang , Te-Yuan Wu , Li-Che Chen , Chih-Chun Pu , Yu-Ting Yeh , Kuan-Wen Lu
发明人： Fu-Chun CHIEN , Ching-Wei Teng , Nien-Chung Li , Chih-Chung Wang , Te-Yuan Wu , Li-Che Chen , Chih-Chun Pu , Yu-Ting Yeh , Kuan-Wen Lu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823481 , H01L21/823418 , H01L21/823493 , H01L27/088
摘要： A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.
摘要翻译：提供一种制造高电压半导体器件的方法。首先，提供衬底，其中衬底具有第一有源区和第二有源区。然后，进行第一离子注入工艺以通过第一掩模层掺杂衬底，从而在第一有源区的两端和第二有源区的周边形成第一极性掺杂区。在去除第一掩模层之后，执行第二离子注入工艺以通过第二掩模层掺杂衬底，从而在第二有源区的两端和第一有源区的周边形成第二极性掺杂区。在去除第二掩模层之后，分别在第一有源区和第二有源区的中间段上形成第一栅极导体结构和第二栅极导体结构。

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