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1. 发明申请

US20180158494A1 SEMICONDUCTOR MEMORY DEVICES, METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS 审中-公开
公开(公告)号：US20180158494A1
公开(公告)日：2018-06-07
申请号：US15656050
申请日：2017-07-21
申请人： MIN-SANG PARK
发明人： MIN-SANG PARK
IPC分类号： G11C7/10 , G11C7/12 , G11C7/22 , G11C7/06 , G11C8/10 , G11C8/18 , G11C5/14
CPC分类号： G11C7/1027 , G11C5/025 , G11C5/063 , G11C5/14 , G11C7/065 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C29/00 , G11C29/46 , G11C2029/0411 , G11C2207/005
摘要： A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.

2. 发明授权

US07714971B2 Liquid crystal display 有权
标题翻译：液晶显示器
公开(公告)号：US07714971B2
公开(公告)日：2010-05-11
申请号：US11545995
申请日：2006-10-10
申请人： Min Sang Park
发明人： Min Sang Park
IPC分类号： G02F1/1345 , G02F1/1339
CPC分类号： G02F1/1345
摘要： A liquid crystal display (LCD) capable of preventing spots from being generated by difference in brightness caused by variation in a gap between substrates is provided. The LCD includes a first pad unit positioned on an upper corner of a lower substrate, a second pad unit positioned on a lower corner of the lower substrate diagonally across from the first pad unit, an integrated circuit electrically connected to the first pad unit and the second pad unit, and dummy pads positioned on the other upper corner of the lower substrate. The dummy pads are substantially symmetrical with second pads included in the second pad unit thus helping maintain the gap between the substrates uniform.
摘要翻译：提供一种能够防止由基板之间的间隙的变化引起的亮度差而产生斑点的液晶显示器（LCD）。 LCD包括位于下基板的上角处的第一焊盘单元，位于下基板的下角的第二焊盘单元，其对角地跨越第一焊盘单元，集成电路，电连接到第一焊盘单元和第二垫单元和位于下基板的另一个上角上的虚拟垫。虚拟焊盘与包括在第二焊盘单元中的第二焊盘基本对称，从而有助于保持基板之间的间隙均匀。

3. 发明授权

US07466608B2 Data input/output circuit having data inversion determination function and semiconductor memory device having the same 有权
标题翻译：具有数据反转确定功能的数据输入/输出电路和具有该数据反转确定功能的半导体存储器件
公开(公告)号：US07466608B2
公开(公告)日：2008-12-16
申请号：US11528799
申请日：2006-09-28
申请人： Min Sang Park
发明人： Min Sang Park
IPC分类号： G11C7/00 , G11C7/02 , G06F13/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C29/02 , G11C29/022
摘要： A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode. According to the data input/output circuit and the semiconductor memory device having the data input/output circuit, it can be readily determined whether a data inversion function is normally performed.
摘要翻译：半导体存储器件的数据输入/输出电路具有数据反转确定功能。在输入模式中，数据输入/输出电路响应输入的反转标志反转输入数据组，并将反相输入数据组发送到存储单元阵列。在输出模式下，当输出数据组满足预定的反转条件时，数据输入/输出电路反转从存储单元阵列输出的数据组，并将反相输出数据组发送到数据输入/输出端电路。在这种情况下，产生表示输出数据组被反转的输出反转标志。此外，数据输入/输出电路以输入模式将输入的反相标志存储在存储单元阵列中，并将存储在存储单元阵列中的输入反相标志与输出模式中的输出反相标志进行比较。根据具有数据输入/输出电路的数据输入/输出电路和半导体存储器件，可以容易地确定数据反转功能是否正常执行。

4. 发明授权

US07408482B2 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
标题翻译：具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
公开(公告)号：US07408482B2
公开(公告)日：2008-08-05
申请号：US11266581
申请日：2005-11-03
申请人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： H03M5/00
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要翻译：集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为分别大于二阶输入数据组的二分之一。

5. 发明申请

US20070103996A1 Data input/output circuit having data inversion determination function and semiconductor memory device having the same 有权
标题翻译：具有数据反转确定功能的数据输入/输出电路和具有该数据反转确定功能的半导体存储器件
公开(公告)号：US20070103996A1
公开(公告)日：2007-05-10
申请号：US11528799
申请日：2006-09-28
申请人： Min Sang Park
发明人： Min Sang Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C29/02 , G11C29/022
摘要： A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode. According to the data input/output circuit and the semiconductor memory device having the data input/output circuit, it can be readily determined whether a data inversion function is normally performed.
摘要翻译：半导体存储器件的数据输入/输出电路具有数据反转确定功能。在输入模式中，数据输入/输出电路响应输入的反转标志反转输入数据组，并将反相输入数据组发送到存储单元阵列。在输出模式下，当输出数据组满足预定的反转条件时，数据输入/输出电路反转从存储单元阵列输出的数据组，并将反相输出数据组发送到数据输入/输出端电路。在这种情况下，产生表示输出数据组被反转的输出反转标志。此外，数据输入/输出电路以输入模式将输入的反相标志存储在存储单元阵列中，并将存储在存储单元阵列中的输入反相标志与输出模式中的输出反相标志进行比较。根据具有数据输入/输出电路的数据输入/输出电路和半导体存储器件，可以容易地确定数据反转功能是否正常执行。

6. 发明授权

US06825511B2 Semiconductor device having fuse circuit on cell region and method of fabricating the same 失效
标题翻译：在单元区域具有熔丝电路的半导体器件及其制造方法
公开(公告)号：US06825511B2
公开(公告)日：2004-11-30
申请号：US10269202
申请日：2002-10-10
申请人： Young-Hee Song , Ill-Heung Choi , Min-Young Son , Min-Sang Park
发明人： Young-Hee Song , Ill-Heung Choi , Min-Young Son , Min-Sang Park
IPC分类号： H01L2710
CPC分类号： H01L24/05 , H01L23/5258 , H01L24/03 , H01L24/45 , H01L24/48 , H01L27/10897 , H01L2224/04042 , H01L2224/05155 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/451 , H01L2224/45144 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.
摘要翻译：提供能够提高集成密度并解决激光修复过程中可能发生的问题的半导体器件及其制造方法。在单元区域中形成熔丝电路，而不是在周边区域，因此可以减小半导体芯片的尺寸。

7. 发明授权

US07525863B2 Logic circuit setting optimization condition of semiconductor integrated circuit regardless of fuse cut 有权
标题翻译：无论保险丝切断，半导体集成电路的逻辑电路设置优化条件
公开(公告)号：US07525863B2
公开(公告)日：2009-04-28
申请号：US11361335
申请日：2006-02-24
申请人： Min-Sang Park
发明人： Min-Sang Park
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.
摘要翻译：提供了一种用于设置半导体电路的优化条件的电路，该半导体电路包括响应于第一控制信号而被配置为产生熔丝切断信号的熔丝切断信号发生器，以及状态设置电路，被配置为响应于多个产生优化信号的状态控制信号和保险丝切断信号。

8. 发明申请

US20060239100A1 Logic circuit setting optimization condition of semiconductor integrated circuit regardless of fuse cut 有权
公开(公告)号：US20060239100A1
公开(公告)日：2006-10-26
申请号：US11361335
申请日：2006-02-24
申请人： Min-Sang Park
发明人： Min-Sang Park
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.

9. 发明申请

US20060209619A1 Data input circuit of synchronous semiconductor memory device using data sampling method for changing DQS domain to clock domain 审中-公开
标题翻译：数据输入电路同步半导体存储器件采用数据采样方式将DQS域变为时钟域
公开(公告)号：US20060209619A1
公开(公告)日：2006-09-21
申请号：US11365653
申请日：2006-03-01
申请人： Min-Sang Park
发明人： Min-Sang Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： Provided is a data input circuit of a semiconductor memory device. The data input circuit includes: an input buffer that samples an external data signal in response to a data strobe signal and outputs a first-sampled signal; a first domain converter that samples the first-sampled signal in response to a first clock signal and outputs a second-sampled signal; and a second domain converter that samples the second-sampled signal in response to a second clock signal containing write command information.
摘要翻译：提供半导体存储器件的数据输入电路。数据输入电路包括：输入缓冲器，其响应于数据选通信号对外部数据信号进行采样，并输出第一采样信号; 第一域转换器，其响应于第一时钟信号对第一采样信号进行采样并输出第二采样信号; 以及响应于包含写入命令信息的第二时钟信号对第二采样信号进行采样的第二域转换器。

10. 发明申请

US20060049851A1 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
标题翻译：具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
公开(公告)号：US20060049851A1
公开(公告)日：2006-03-09
申请号：US11266581
申请日：2005-11-03
申请人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： H03K19/094
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要翻译：集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为分别大于二阶输入数据组的二分之一。

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