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1. 发明授权

US5801554A Semiconductor Integrated circuit device for handling low amplitude signals 失效
标题翻译：用于处理低振幅信号的半导体集成电路器件
公开(公告)号：US5801554A
公开(公告)日：1998-09-01
申请号：US674917
申请日：1996-07-03
申请人： Atsuko Momma , Miki Matsumoto , Kanji Oishi
发明人： Atsuko Momma , Miki Matsumoto , Kanji Oishi
IPC分类号： G11C11/407 , G11C11/401 , G11C11/409 , H03K5/135 , H03K19/0185
CPC分类号： G11C11/4076 , G11C11/4082 , G11C11/4093 , G11C7/1084
摘要： A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.
摘要翻译：提供一种具有低振幅输入/输出接口的半导体集成电路器件，用于与时钟信号同步地输入或输出输入/输出信号，并以与电源电压相对应的幅度传送输入/输出信号外部命令单位。将实际上连续操作的第一差分电路用作接收从外部时钟单元提供的时钟信号的输入电路。此外，提供第二差分电路，其根据时钟信号间歇地操作，以在第二差分电路被操作的同时根据第一差分电路产生的内部时钟信号对输入信号进行采样，并保持采样信号，同时第二差分电路不工作。该第二差分电路用作接收与时钟信号同步输入的低振幅输入信号的输入电路。

2. 发明授权

US5598372A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5598372A
公开(公告)日：1997-01-28
申请号：US507604
申请日：1995-07-25
申请人： Miki Matsumoto , Kanji Oishi , Masahiro Katayama , Kazufumi Watanabe
发明人： Miki Matsumoto , Kanji Oishi , Masahiro Katayama , Kazufumi Watanabe
IPC分类号： G11C11/401 , G06F12/00 , G06F12/02 , G09G5/393 , G11C7/10 , G11C8/00 , G11C11/407 , G11C13/00
CPC分类号： G09G5/393 , G11C7/1006 , G11C8/00
摘要： A semiconductor memory incorporating an operation circuit for carrying out logical operations on data and arithmetic operations on address signals. The memory is arranged functionally so that the data representing the result of each of such operations is written to a memory array while also being output through an external terminal in the same memory cycle.
摘要翻译：一种半导体存储器，其包含用于对地址信号进行数据和算术运算的逻辑运算的运算电路。存储器功能地布置，使得表示每个这样的操作的结果的数据被写入存储器阵列，同时也通过外部终端在相同的存储器周期中输出。

3. 发明授权

US5313423A Semiconductor memory device 失效
公开(公告)号：US5313423A
公开(公告)日：1994-05-17
申请号：US754019
申请日：1991-09-03
申请人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
发明人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04 , G11C13/00
CPC分类号： G11C7/18 , G11C7/1075 , G11C8/10
摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

4. 发明授权

US5278839A Semiconductor integrated circuit having self-check and self-repair capabilities 失效
标题翻译：具有自检和自修复功能的半导体集成电路
公开(公告)号：US5278839A
公开(公告)日：1994-01-11
申请号：US693911
申请日：1991-04-16
申请人： Miki Matsumoto , Hiroshi Kawamoto
发明人： Miki Matsumoto , Hiroshi Kawamoto
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/76 , G11C29/835
摘要： A semiconductor integrated circuit which has the function of self-checking defective bits, and which informs the exterior of its status when it has reached the status incapable of self-repair due to the limitation of the storage capacity of hardware for repairing the defective bits.
摘要翻译：具有自检缺陷位的功能的半导体集成电路，由于修复缺陷位的硬件的存储容量的限制，当半导体集成电路达到不能进行自修复的状态时，该状态通知外部状态。

5. 发明授权

US5436870A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5436870A
公开(公告)日：1995-07-25
申请号：US283177
申请日：1994-08-03
申请人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
发明人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04 , G11C11/40 , G11C13/00
CPC分类号： G11C7/18 , G11C7/1075 , G11C8/10
摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.
摘要翻译：提供多端口存储器，允许随机访问和串行访问。为了减少寄生电容并提高工作速度，串行输入/输出线在其中间点分为两部分。用于串行输入/输出线的读出放大器设置在串行存取存储器元件的上端和下端，以分别放大来自分割线的信号。提供了另外的功能来改进串行和随机操作。例如，在串行读取模式期间，用于随机存取的列选择器被同时操作，并且通过随机存取列选择器的读数据被用作通过串行输出电路传送的串行输出操作的头数据。此外，串行选择器可以由格雷码计数器形成的选择信号控制，以提高操作速度。其他特征包括用于缓解缺陷位的冗余系统，使用公共位线来提高集成密度以及改进的刷新布置以减少刷新模式期间的功耗。

6. 发明授权

US5323033A Single chip IC device having gate array or memory with gate array and provided with redundancy capability 失效
标题翻译：具有门阵列或具有门阵列的存储器并具有冗余能力的单芯片IC器件
公开(公告)号：US5323033A
公开(公告)日：1994-06-21
申请号：US921962
申请日：1992-08-04
申请人： Miki Matsumoto , Hiroshi Kawamoto
发明人： Miki Matsumoto , Hiroshi Kawamoto
IPC分类号： H01L21/82 , H01L27/118 , H01L27/02
CPC分类号： H01L27/118
摘要： The present invention disposes a redundancy logic device and a redundancy line which are used selectively in place of a logic device or a line, which becomes unusable, in a logic portion of a semiconductor integrated circuit device such as a gate array integrated circuit.
摘要翻译：本发明在诸如门阵列集成电路的半导体集成电路器件的逻辑部分中配置冗余逻辑器件和冗余线，所述冗余逻辑器件和冗余线选择性地代替逻辑器件或线路，其变得不可用。

7. 发明授权

US5115413A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5115413A
公开(公告)日：1992-05-19
申请号：US496258
申请日：1990-03-20
申请人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
发明人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04
CPC分类号： G11C7/18 , G11C7/1075 , G11C8/10
摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features include a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.
摘要翻译：提供多端口存储器，允许随机访问和串行访问。为了减少寄生电容并提高工作速度，串行输入/输出线在其中间点分为两部分。用于串行输入/输出线的读出放大器设置在串行存取存储器元件的上端和下端，以分别放大来自分割线的信号。提供了另外的功能来改进串行和随机操作。例如，在串行读取模式期间，用于随机存取的列选择器被同时操作，并且通过随机存取列选择器的读数据被用作通过串行输出电路传送的串行输出操作的头数据。此外，串行选择器可以由格雷码计数器形成的选择信号控制，以提高操作速度。其他特征包括用于缓解缺陷位的冗余系统，使用公共位线来提高集成密度，以及改进的刷新布置以减少刷新模式期间的功耗。

8. 发明授权

US5497353A Semiconductor memory device 失效
公开(公告)号：US5497353A
公开(公告)日：1996-03-05
申请号：US413411
申请日：1995-03-30
申请人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
发明人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04 , G11C13/00
CPC分类号： G11C7/18 , G11C7/1075 , G11C8/10
摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

9. 发明授权

US5323354A Semiconductor memory device including arrangements to facilitate battery backup 失效
标题翻译：半导体存储器件包括便于电池备份的布置
公开(公告)号：US5323354A
公开(公告)日：1994-06-21
申请号：US836597
申请日：1992-02-18
申请人： Miki Matsumoto , Katsuyuki Sato
发明人： Miki Matsumoto , Katsuyuki Sato
IPC分类号： G06F12/16 , G05F3/24 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4074 , G11C11/408 , H03K3/01
CPC分类号： G11C5/141 , G05F3/24 , G11C11/406 , G11C11/4074 , G11C11/4085
摘要： A multi-port memory is provided which is capable of being backed up by a battery to provide a resume function for a digital processor. In a preferred embodiment, a resume function can be provided for a VRAM without restricting the bit rate of image data or the function of the frame memory. Preferably, the memory includes a memory array MARY of memory cells of stereoscopic structure. A high voltage VCH for word line selection can be generated by a voltage-doubling word boost circuit which has its boosting ratio switched stepwise in accordance with the potential of an internal supply voltage. Moreover, a substrate potential generator is provided which has a first substrate potential generator having a relatively low current supplying capacity, which is steadily brought into an operative state, and a second substrate potential generator having a relatively high current supplying capacity which is selectively brought into an operative state. During battery backup, the multi-port memory is in a self-refresh memory. Also, the number of memory mats to be simultaneously activated in the self-refresh mode is made larger than that in the ordinary mode, and a refresh timer circuit RTM for setting the refresh period is of a diffusion layer leakage type.
摘要翻译：提供了能够由电池备份以提供数字处理器的恢复功能的多端口存储器。在优选实施例中，可以为VRAM提供恢复功能，而不限制图像数据的比特率或帧存储器的功能。优选地，存储器包括立体结构的存储器单元的存储器阵列MARY。用于字线选择的高电压VCH可以通过倍压字升压电路产生，该升压电路的升压比根据内部电源电压的电位逐步切换。此外，提供了具有稳定地进入操作状态的具有相对低的电流供应能力的第一衬底电位发生器的衬底电位发生器和具有相对高的电流供应能力的第二衬底电位发生器，该第二衬底电位发生器选择性地被引入操作状态在备份电池期间，多端口存储器处于自刷新存储器中。而且，在自刷新模式下同时激活的存储器垫的数量大于普通模式，并且用于设置刷新周期的刷新定时器电路RTM具有扩散层泄漏型。

10. 发明授权

US5289428A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5289428A
公开(公告)日：1994-02-22
申请号：US972913
申请日：1992-11-06
申请人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
发明人： Katsuyuki Sato , Miki Matsumoto , Sadayuki Ohkuma , Masahiro Ogata , Masahiro Yoshida
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04 , G11C13/00
CPC分类号： G11C7/18 , G11C7/1075 , G11C8/10
摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.
摘要翻译：提供多端口存储器，允许随机访问和串行访问。为了减少寄生电容并提高工作速度，串行输入/输出线在其中间点分为两部分。用于串行输入/输出线的读出放大器设置在串行存取存储器元件的上端和下端，以分别放大来自分割线的信号。提供了另外的功能来改进串行和随机操作。例如，在串行读取模式期间，用于随机存取的列选择器被同时操作，并且通过随机存取列选择器的读数据被用作通过串行输出电路传送的串行输出操作的头数据。此外，串行选择器可以由格雷码计数器形成的选择信号控制，以提高操作速度。其他特征包括用于缓解缺陷位的冗余系统，使用公共位线来提高集成密度以及改进的刷新布置以减少刷新模式期间的功耗。

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