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1. 发明授权

US08533395B2 Moveable locked lines in a multi-level cache 有权
标题翻译：多级缓存中的可移动锁定行
公开(公告)号：US08533395B2
公开(公告)日：2013-09-10
申请号：US11361228
申请日：2006-02-24
申请人： Dennis M. O'Connor , Michael W. Morrow , Stephen J. Strazdus
发明人： Dennis M. O'Connor , Michael W. Morrow , Stephen J. Strazdus
IPC分类号： G06F12/14
CPC分类号： G06F12/0811 , G06F12/0871 , G06F12/0888 , G06F12/126 , G06F12/128
摘要： A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.
摘要翻译：处理器包括多级缓存层级，其中锁属性与高速缓存线相关联。缓存行保留锁定属性，并且可以在缓存层次结构内来回移动。在锁定属性被删除后，缓存行可以从缓存层次结构中逐出。

2. 发明授权

US07822925B2 Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions 有权
标题翻译：低功耗半跟踪指令/跟踪混合高速缓存，具有用于在特定条件下对跟踪缓存进行索引的逻辑
公开(公告)号：US07822925B2
公开(公告)日：2010-10-26
申请号：US12200474
申请日：2008-08-28
申请人： Michael W. Morrow
发明人： Michael W. Morrow
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3814 , G06F12/0875
摘要： A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution.
摘要翻译：半跟踪缓存组合指令高速缓存和跟踪高速缓存的元素和特征。半跟踪缓存的ICache部分填充有从内存层次结构的下一级获取的指令，而TCache部分填充了从实际的退出指令流或执行之前预测的跟踪。

3. 发明授权

US07596683B2 Switching processor threads during long latencies 有权
标题翻译：在长时间延迟期间切换处理器线程
公开(公告)号：US07596683B2
公开(公告)日：2009-09-29
申请号：US11827207
申请日：2007-07-11
申请人： Michael W. Morrow
发明人： Michael W. Morrow
IPC分类号： G06F9/44
CPC分类号： G06F9/3851
摘要： In one embodiment, the present invention includes an apparatus to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the instruction may require the long latency. In certain embodiments, at least one additional instruction may be executed in the first thread while preparing to switch threads.
摘要翻译：在一个实施例中，本发明包括一种用于确定第一线程的指令的执行是否可能需要长延迟并且如果该指令可能需要长延迟则切换到第二线程的装置。在某些实施例中，在准备切换线程时，可以在第一线程中执行至少一个附加指令。

4. 发明授权

US07472390B2 Method and apparatus to enable execution of a thread in a multi-threaded computer system 失效
标题翻译：能够在多线程计算机系统中执行线程的方法和装置
公开(公告)号：US07472390B2
公开(公告)日：2008-12-30
申请号：US10677913
申请日：2003-10-01
申请人： Dennis M. O'Connor , Michael W. Morrow
发明人： Dennis M. O'Connor , Michael W. Morrow
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： Briefly, in accordance with an embodiment of the invention, an apparatus and method to enable execution of a thread in a multi-threaded computer system is provided. The method may include enabling execution of a non-executing thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread. The apparatus may include a thread dispatch circuit to enable execution of a pending thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread.
摘要翻译：简而言之，根据本发明的实施例，提供了一种能够执行多线程计算机系统中的线程的装置和方法。该方法可以包括至少基于硬件资源是否可用于非执行线程的指令来执行非执行线程的执行。该装置可以包括线程调度电路，以便至少基于硬件资源是否可用于非执行线程的指令来执行挂起线程。

5. 发明授权

US07581065B2 Low locality-of-reference support in a multi-level cache hierachy 有权
标题翻译：多级缓存层级中的低地理位置参考支持
公开(公告)号：US07581065B2
公开(公告)日：2009-08-25
申请号：US11101785
申请日：2005-04-07
申请人： Dennis M. O'Connor , Michael W. Morrow
发明人： Dennis M. O'Connor , Michael W. Morrow
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/0897 , G06F12/128
摘要： A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.
摘要翻译：处理器包括多级缓存层级，其中诸如低位置参考（LLR）属性的位置信息属性与高速缓存行相关联。 LLR高速缓存行保留位置信息，并且可以在高速缓存层级内来回移动，直到从高速缓存层次结构的最外层级逐出。

6. 发明申请

US20090013131A1 LOW POWER SEMI-TRACE INSTRUCTION CACHE 有权
标题翻译：低功率半导体指令高速缓存
公开(公告)号：US20090013131A1
公开(公告)日：2009-01-08
申请号：US12200474
申请日：2008-08-28
申请人： Michael W. MORROW
发明人： Michael W. MORROW
IPC分类号： G06F12/08
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3814 , G06F12/0875
摘要： A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution.
摘要翻译：半跟踪缓存组合指令高速缓存和跟踪高速缓存的元素和特征。半跟踪缓存的ICache部分填充有从内存层次结构的下一级获取的指令，而TCache部分填充了从实际的退出指令流或执行之前预测的跟踪。

7. 发明授权

US06949918B2 Apparatus having adjustable operational modes and method therefore 有权
标题翻译：因此，具有可调节的操作模式和方法的装置
公开(公告)号：US06949918B2
公开(公告)日：2005-09-27
申请号：US10459310
申请日：2003-06-10
申请人： Lawrence T. Clark , Michael W. Morrow , Gregory B. Tucker , Yuan-Po Ypt Tseng , Ali Minaei , Jay Heeb
发明人： Lawrence T. Clark , Michael W. Morrow , Gregory B. Tucker , Yuan-Po Ypt Tseng , Ali Minaei , Jay Heeb
IPC分类号： G06F1/04 , G06F1/32 , G05F1/40 , G05F1/44
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.
摘要翻译：简而言之，根据本发明的一个实施例，集成电路具有电压调节器和时钟分频器，其可用于调整集成电路的工作频率和/或电压电位以降低集成电路的功耗，同时在运行。

8. 发明授权

US08856448B2 Methods and apparatus for low intrusion snoop invalidation 有权
标题翻译：低入侵窥探无效的方法和装置
公开(公告)号：US08856448B2
公开(公告)日：2014-10-07
申请号：US12388545
申请日：2009-02-19
申请人： Michael W. Morrow , James Norris Dieffenderfer
发明人： Michael W. Morrow , James Norris Dieffenderfer
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/0808 , Y02D10/13
摘要： Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.
摘要翻译：描述了用于跟踪需要一致性的数据高速缓存中的数据高速缓存条目的潜在无效的高效技术。一致性信息被接收，指示数据高速缓存条目的潜在无效。与数据高速缓存条目相关联的一致性信息被保留以跟踪对数据高速缓存条目的潜在无效。保留的一致性信息与在缓存访问操作中使用的状态位分开。与数据高速缓存条目相关联的无效位可用于表示数据高速缓存条目的潜在无效。响应于一致性信息设置无效位以跟踪数据高速缓存条目的潜在无效。响应于活动无效位和存储器同步命令来设置与数据高速缓存条目相关联的有效位。置位无效位在有效位清零后清零。

9. 发明授权

US08112643B2 Methods and apparatus to selectively power functional units 有权
标题翻译：选择性地为功能单元供电的方法和装置
公开(公告)号：US08112643B2
公开(公告)日：2012-02-07
申请号：US12232646
申请日：2008-09-22
申请人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
发明人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
IPC分类号： G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3287 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1028 , Y02D10/13 , Y02D10/171
摘要： A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
摘要翻译：处理引擎将一行或多行软件指令读取到指令高速缓存中。基于高速缓存的内容，可能需要的功能单元被识别为可操作以执行存储在指令高速缓存内的至少一个软件指令的功能单元。不需要的功能单元被识别为不能用于执行存储在指令高速缓存内的软件指令的功能单元。对被确定为处于低功率状态的潜在需要的功能单元中的所选择的功能单元启动功率增加。对被确定为处于可操作功率状态的不需要的功能单元中的所选功能单元启动功率减小。

10. 发明申请

US20090037753A1 Methods and apparatus to selectively power functional units 有权
标题翻译：选择性地为功能单元供电的方法和装置
公开(公告)号：US20090037753A1
公开(公告)日：2009-02-05
申请号：US12232646
申请日：2008-09-22
申请人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
发明人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
IPC分类号： G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3287 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1028 , Y02D10/13 , Y02D10/171
摘要： A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
摘要翻译：处理引擎将一行或多行软件指令读取到指令高速缓存中。基于高速缓存的内容，可能需要的功能单元被识别为可操作以执行存储在指令高速缓存内的至少一个软件指令的功能单元。不需要的功能单元被识别为不能用于执行存储在指令高速缓存内的软件指令的功能单元。对被确定为处于低功率状态的潜在需要的功能单元中的所选择的功能单元启动功率增加。对被确定为处于可操作功率状态的不需要的功能单元中的所选功能单元启动功率减小。

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