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1. 发明授权

US4816700A Two-phase non-overlapping clock generator 失效
标题翻译：两相非重叠时钟发生器
公开(公告)号：US4816700A
公开(公告)日：1989-03-28
申请号：US133325
申请日：1987-12-16
申请人： Michael T. Imel
发明人： Michael T. Imel
IPC分类号： H03K5/15 , H03K5/151 , H03K5/13 , H03K19/00
CPC分类号： H03K5/1515 , H03K5/1506
摘要： An external timing source (40) provides an input waveform (44, 46) of signal voltage transitions which occur at a first frequency, which is twice the frequency desired by the internal clock. A divider circuit (48) divides the input waveform (44, 46) into a pair of intermediate waveforms (60, 62). The intermediate waveforms have signal-voltage transitions of opposing polarity which occur at a second frequency that is one-half of the first frequency. The input waveforms and the intermediate waveforms are supplied to a driver circuit (64). The driver circuit utilizes the intermediate waveforms occurring at the divided-down frequency and the input waveform occurring at the system clock frequency to produce a pair of final waveforms (66, 68). The final waveforms have signal voltage transistions of opposing polarity occurring at the divided-down frequency, but triggerred by and in synchronism with the input waveform occurring at the external clock frequency.
摘要翻译：外部定时源（40）提供以第一频率发生的信号电压转换的输入波形（44,46），其是内部时钟所需频率的两倍。分频电路（48）将输入波形（44,46）分成一对中间波形（60,62）。中间波形具有相反极性的信号电压转换，其以第一频率的二分之一的第二频率发生。输入波形和中间波形被提供给驱动器电路（64）。驱动器电路利用在分频下产生的中间波形和在系统时钟频率处出现的输入波形，产生一对最终波形（66,68）。最终波形具有相反极性的信号电压转换，发生在分频频率处，但由外部时钟频率发生的输入波形触发并与其同步。

2. 发明授权

US5758134A Microprocessor embedded control system having an automatic clock slowdown circuit 失效
标题翻译：微处理器嵌入式控制系统具有自动时钟减速电路
公开(公告)号：US5758134A
公开(公告)日：1998-05-26
申请号：US711721
申请日：1996-09-04
申请人： Michael T. Imel , Bohdan Y. Tashchuk
发明人： Michael T. Imel , Bohdan Y. Tashchuk
IPC分类号： G06F1/04 , G06F1/24 , G06F1/12
CPC分类号： G06F1/24 , G06F1/04
摘要： An embedded microprocessor control system temporarily slows a microprocessor clock input signal in response to a reset strobe. This permits the peripherals to synchronize the classification of their clock phases with 386 microprocessor clock phase classifications.
摘要翻译：嵌入式微处理器控制系统会暂时减慢微处理器时钟输入信号，以响应复位选通信号。这允许外设使其时钟相位的分类与386个微处理器时钟相位分类同步。

3. 发明授权

US4891753A Register scorboarding on a microprocessor chip 失效
标题翻译：在微处理器芯片上注册scorboarding
公开(公告)号：US4891753A
公开(公告)日：1990-01-02
申请号：US935193
申请日：1986-11-26
申请人： David Budde , Robert Riches , Michael T. Imel , Glen Myers , Konrad Lai
发明人： David Budde , Robert Riches , Michael T. Imel , Glen Myers , Konrad Lai
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836
摘要： When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.
摘要翻译：当遇到加载指令时，读操作被发送到总线控制逻辑，寄存器被标记为忙，并且执行进行到下一条指令。当执行指令时，继续执行其源和目标寄存器未标记为忙; 否则将重试该指令。当作为读取操作的结果返回数据时，目标寄存器被标记为不忙。

4. 发明授权

US4811208A Stack frame cache on a microprocessor chip 失效
标题翻译：微处理器芯片上的堆栈缓存
公开(公告)号：US4811208A
公开(公告)日：1989-03-07
申请号：US863878
申请日：1986-05-16
申请人： Glenford J. Myers , Konrad Lai , Michael T. Imel , Glenn Hinton , Robert Riches
发明人： Glenford J. Myers , Konrad Lai , Michael T. Imel , Glenn Hinton , Robert Riches
IPC分类号： G06F9/42 , G06F9/30 , G06F9/40 , G06F9/46 , G06F12/08
CPC分类号： G06F9/3013 , G06F9/3012 , G06F9/30127 , G06F9/30134 , G06F9/4425 , G06F9/462 , G06F2212/451
摘要： A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.
摘要翻译：在微处理器芯片上提供多个全局寄存器。全局寄存器之一是包含当前帧指针的帧指针寄存器，其余的全局寄存器作为通用寄存器可用于当前进程。还提供了多个浮点寄存器供当前进程在浮点算术运算中使用。提供由多个寄存器组构成的寄存器组池，每个寄存器组由多个本地寄存器组成。当调用指令被解码时，寄存器组池的本地寄存器的寄存器组被分配给被调用的程序，并且帧指针寄存器被初始化。当返回指令被解码时，寄存器组被释放以分配给由后续调用指令调用的另一过程。如果寄存器集合池耗尽，则与先前过程相关联的寄存器集保存在主存储器中，并且该寄存器集被分配给当前过程。与过程相关联的寄存器集中的本地寄存器包含链接信息，包括指向前一帧的指针和指令指针，从而使得大多数调用和返回指令执行而不需要对片外存储器的任何引用。

5. 发明授权

US4823260A Mixed-precision floating point operations from a single instruction opcode 失效
标题翻译：来自单指令操作码的混合精度浮点运算
公开(公告)号：US4823260A
公开(公告)日：1989-04-18
申请号：US119547
申请日：1987-11-12
申请人： Michael T. Imel , Konrad Lai , Glenford J. Myers , Randy Steck , James Valerio
发明人： Michael T. Imel , Konrad Lai , Glenford J. Myers , Randy Steck , James Valerio
IPC分类号： G06F7/57 , G06F7/48
CPC分类号： G06F7/483 , G06F2207/3816 , G06F7/49957
摘要： Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.
摘要翻译：用于从单个指令操作码在微处理器的浮点单元中执行混合精度计算的装置。可以将80位浮点寄存器（44）指定为浮点指令的源地址或目标地址。当目的地的地址范围指示（26）指定浮点寄存器时，该操作的结果不会舍入到指令指定的精度，而是舍入（58）到扩展的80位精度并加载到浮点寄存器（FP-44）。当源地址范围指示（26）FP寄存器被寻址时，无论指令指定的精度如何，数据都以扩展精度从FP寄存器加载。以这种方式，可以使用实际和长期实际的操作来使用扩展精度数字，而无需在操作码中明确指定。

6. 发明授权

US4694425A Seven transistor content addressable memory (CAM) cell 失效
标题翻译：七晶体管内存可寻址存储器（CAM）单元
公开(公告)号：US4694425A
公开(公告)日：1987-09-15
申请号：US884025
申请日：1986-07-10
申请人： Michael T. Imel
发明人： Michael T. Imel
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged. The memory cell is comprised of transistors (M1, M2, M3, M4) connected to each other and to a supply voltage (Vcc) to thereby form a cross-coupled inverter storage device. Transistors (M5, M6) are connected to diode transistor (M7) and between the cross-coupled inverter (M1, M2, M3, M4) and column lines (54, 56) to thereby form and XOR gate on said column lines (54, 56) and diode transistor (M7). The diode transistor is connected between transistors (M5, M6), ROW line (50) and MATCH line (52), such that during CAM matches the diode transistor allows charge to be siphoned from MATCH line ( 52) and during a write to said CAM cell allows charge to build up.
摘要翻译：一种内容可寻址存储器，包括一对列线（54,56），在其上放置与所述存储器的内容匹配的信息。存储器由时钟驱动，使得在特定时钟相位期间，ROW线（50）和匹配线（52）被预充电并且两列都被放电。存储单元包括彼此连接的电压和电源电压（Vcc）的晶体管（M1，M2，M3，M4），从而形成交叉耦合的逆变器存储装置。晶体管（M5，M6）连接到二极管晶体管（M7）和交叉耦合的反相器（M1，M2，M3，M4）和列线（54,56）之间，从而在所述列线（54）上形成XOR栅极，56）和二极管晶体管（M7）。二极管晶体管连接在晶体管（M5，M6），ROW线（50）和MATCH线（52）之间，使得在CAM匹配期间，二极管晶体管允许电荷从MATCH线（52）虹吸，并且在写入所述 CAM单元可以进行充电。

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