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1. 发明授权

US07966480B2 Register pointer trap to prevent errors due to an invalid pointer value in a register 有权
标题翻译：寄存器指针陷阱以防止由于寄存器中的无效指针值引起的错误
公开(公告)号：US07966480B2
公开(公告)日：2011-06-21
申请号：US11016798
申请日：2004-12-20
申请人： Michael I. Catherwood
发明人： Michael I. Catherwood
IPC分类号： G06F9/00
CPC分类号： G06F9/30101 , G06F9/34 , G06F9/3861 , G06F11/004
摘要： Trap flags and a pointer trap are associated with registers in a processor. Each trap flag indicates whether a corresponding register has been written with valid data. If not, the trap flag is set to indicate that the register corresponding to the trap flag contains invalid data. During instruction processing, the pointer trap receives control signals from instruction fetch/decode logic on the processor indicating an instruction being processed calls for a register to be used as a pointer. If the specified pointer register has its corresponding trap flag set, then the pointer trap indicates that a processing exception has occurred. The interrupt logic/exception processing logic then causes a trap interrupt service routine (ISR) to be executed in response to the exception. The ISR prevents errors from being introduced in the instruction processing due to invalid pointer values.
摘要翻译：陷阱标志和指针陷阱与处理器中的寄存器相关联。每个陷阱标志指示相应的寄存器是否已写入有效数据。如果没有，陷阱标志设置为指示对应于陷阱标志的寄存器包含无效数据。在指令处理期间，指针陷阱从处理器上的指令获取/解码逻辑接收控制信号，指示正被处理的指令将要用作指针的寄存器。如果指定的指针寄存器设置了相应的陷阱标志，则指针trap指示发生处理异常。然后，中断逻辑/异常处理逻辑使得针对异常执行陷阱中断服务程序（ISR）。 ISR防止由于无效指针值而在指令处理中引入错误。

2. 发明授权

US5680632A Method for providing an extensible register in the first and second data processing systems 失效
标题翻译：在第一和第二数据处理系统中提供可扩展寄存器的方法
公开(公告)号：US5680632A
公开(公告)日：1997-10-21
申请号：US996744
申请日：1992-12-24
申请人： Charles F. Studor , James S. Divine , Michael I. Catherwood
发明人： Charles F. Studor , James S. Divine , Michael I. Catherwood
IPC分类号： G06F9/34 , G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F5/00
CPC分类号： G06F9/342 , G06F9/30101 , G06F9/30112
摘要： A data processing system providing an extensible register and method thereof. A new CPU has an extensible index register. The new CPU is object code compatible with the old CPU having an 8-bit index register, yet the index register of the new CPU can be effectively extended to 16 bits when new instructions are used. As a consequence, the user is able to make the choice between using assembly code software written for the old CPU and having the functionality of an 8-bit index register, or writing new assembly code software for the new CPU and having the functionality of a 16-bit index register.
摘要翻译：一种提供可扩展寄存器的数据处理系统及其方法。新的CPU具有可扩展的索引寄存器。新的CPU是与具有8位索引寄存器的旧CPU兼容的目标代码，而当使用新的指令时，新CPU的索引寄存器可以有效地扩展到16位。因此，用户能够在使用为旧CPU编写的汇编代码软件和具有8位索引寄存器的功能之间进行选择，或为新CPU编写新的汇编代码软件，并具有 16位索引寄存器。

3. 发明授权

US08688964B2 Programmable exception processing latency 有权
标题翻译：可编程异常处理延迟
公开(公告)号：US08688964B2
公开(公告)日：2014-04-01
申请号：US12776513
申请日：2010-05-10
申请人： Michael I. Catherwood , David Mickey
发明人： Michael I. Catherwood , David Mickey
IPC分类号： G06F9/44
CPC分类号： G06F13/24
摘要： A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with the CPU, and a control register coupled with the CPU, wherein the control register is operable to set the operation mode of the CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time.
摘要翻译：具有可编程异常处理延迟的数字处理器可以具有数字处理器的中央处理单元（CPU），与CPU耦合的异常控制器以及与CPU耦合的控制寄存器，其中控制寄存器可操作以设置操作在两种模式中的至少一种模式下，CPU在第一模式中具有固定的异常处理等待时间，而在第二模式中，CPU具有可变异常处理等待时间。

4. 发明申请

US20110022756A1 Data Space Arbiter 有权
标题翻译：数据空间仲裁器
公开(公告)号：US20110022756A1
公开(公告)日：2011-01-27
申请号：US12818325
申请日：2010-06-18
申请人： Michael I. Catherwood , Ashish Desai
发明人： Michael I. Catherwood , Ashish Desai
IPC分类号： G06F13/30
CPC分类号： G06F13/1605 , G06F13/362
摘要： A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.
摘要翻译：数字处理器具有在默认模式下具有最高优先级的默认总线主机，具有相关优先级的多个辅助总线主机，其中所述多个辅助总线主机彼此具有预定的优先级关系，以及数据空间仲裁器。数据空间仲裁器可在非默认模式下编程，以提高任何副总线主机的优先级，使其优先级高于默认总线主机的优先级，同时将预定的优先级关系保持在仅与那些辅助总线主机优先级也高于默认总线主控的优先级。

5. 发明授权

US07020788B2 Reduced power option 有权
公开(公告)号：US07020788B2
公开(公告)日：2006-03-28
申请号：US09870772
申请日：2001-06-01
申请人： Michael I. Catherwood
发明人： Michael I. Catherwood
IPC分类号： G06F1/32
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30116 , G06F9/30123 , G06F9/345 , G06F9/3824 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.

6. 发明授权

US06934728B2 Euclidean distance instructions 有权
标题翻译：欧几里德距离说明
公开(公告)号：US06934728B2
公开(公告)日：2005-08-23
申请号：US09870649
申请日：2001-06-01
申请人： Michael I. Catherwood
发明人： Michael I. Catherwood
IPC分类号： G06F7/00 , G06F7/38 , G06F7/52 , G06F7/552 , G06F9/30 , G06F9/302 , G06F15/00
CPC分类号： G06F7/552 , G06F9/3001 , G06F9/30094
摘要： A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The multiplication operation instructions are provided to perform complex multiplication operations. The multiplication operation instructions may generate the square of a multiplication source operand and generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The square is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction. In the alternative, the multiplication operation instructions may generate the sum of the square of multiplication source operand and an addition operand as well as generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The sum is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction.
摘要翻译：提供了一种用于乘法运算指令处理的方法和处理器。对数据存储单元中的源操作数执行乘法运算指令。提供乘法运算指令以执行复数乘法运算。乘法运算指令可以生成乘法运算源的平方，并且同时生成减法源操作数和最小源操作数的差值。该方形输出到乘法运算指令中指定的目标累加器。差值输出到乘法运算指令中指定的差分寄存器。或者，乘法运算指令可以生成乘法运算部的平方和加法运算的和，并且同时生成减法源操作数和减法源操作数的差。该和输出到乘法运算指令中指定的目标累加器。差值输出到乘法运算指令中指定的差分寄存器。

7. 发明授权

US06604169B2 Modulo addressing based on absolute offset 有权
公开(公告)号：US06604169B2
公开(公告)日：2003-08-05
申请号：US09870445
申请日：2001-06-01
申请人： Michael I. Catherwood
发明人： Michael I. Catherwood
IPC分类号： G06F1206
CPC分类号： G06F7/72 , G06F5/10
摘要： A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.

8. 发明授权

US5854944A Method and apparatus for determining wait states on a per cycle basis in a data processing system 失效
标题翻译：用于在数据处理系统中基于每个周期确定等待状态的方法和装置
公开(公告)号：US5854944A
公开(公告)日：1998-12-29
申请号：US645014
申请日：1996-05-09
申请人： Michael I. Catherwood , Norrie R. Robertson , Gordon W. McKinnon
发明人： Michael I. Catherwood , Norrie R. Robertson , Gordon W. McKinnon
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： Method and apparatus in a data processing system (10) for determining wait states on a per cycle basis. The present invention provides a wait state value (39) to a data processing system (10) indicating the number of wait states for each bus cycle. In one embodiment, a wait state pulse (81) is provided by data processing system (10), during which the wait state value (39) is provided to data processing system (10) by way of data bus (82). In response to the wait state value (39), data processing system (10) inserts a number of wait states corresponding to the wait state value (39) during the present bus cycle. In one embodiment of the present invention, a chip select signal (73) is combined with a portion of the address (83) to further partition the address range of the chip select signal (73).
摘要翻译：一种数据处理系统（10）中用于基于每个周期确定等待状态的方法和装置。本发明向数据处理系统（10）提供指示每个总线周期的等待状态数量的等待状态值（39）。在一个实施例中，等待状态脉冲（81）由数据处理系统（10）提供，其间通过数据总线（82）将等待状态值（39）提供给数据处理系统（10）。响应于等待状态值（39），数据处理系统（10）在当前总线周期期间插入与等待状态值（39）对应的多个等待状态。在本发明的一个实施例中，芯片选择信号（73）与地址（83）的一部分组合以进一步分割片选信号（73）的地址范围。

9. 发明申请

US20100306292A1 DSP Engine with Implicit Mixed Sign Operands 有权
标题翻译：具有隐式混合符号操作数的DSP引擎
公开(公告)号：US20100306292A1
公开(公告)日：2010-12-02
申请号：US12776193
申请日：2010-05-07
申请人： Michael I. Catherwood , Settu Duraisamy
发明人： Michael I. Catherwood , Settu Duraisamy
IPC分类号： G06F7/52 , G06F5/01
CPC分类号： G06F9/30014 , G06F7/49921 , G06F7/49994 , G06F7/53 , G06F7/5324 , G06F9/30112 , G06F9/30189 , G06F2207/3812
摘要： A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
摘要翻译：处理器可以具有至少一个乘法器单元，其可以被控制以在签名，无符号或混合符号模式中操作; 与所述乘法器单元耦合的乘法器模式解码器，其接收第一和第二操作数的位置信息，其中所述乘法器模式解码器根据所述位置信息以混合符号模式控制所述乘法器单元以在有符号模式下操作，无符号模式或组合有符号/无符号模式。

10. 发明授权

US5535376A Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor 失效
标题翻译：数据处理器具有用于执行缓冲脉宽调制功能的定时器电路及其方法
公开(公告)号：US5535376A
公开(公告)日：1996-07-09
申请号：US62625
申请日：1993-05-18
申请人： Michael I. Catherwood , Kevin Kilbane , Laura M. Dobbs
发明人： Michael I. Catherwood , Kevin Kilbane , Laura M. Dobbs
IPC分类号： G06F1/14 , G06F1/04
CPC分类号： G06F1/14
摘要： A timer (28) uses two output-compare timer channels to form a buffered pulse width modulator. A first register (62) and a second register are provided to store a first pulse width value and a second register (66), respectively. When the first register (62) is written to, a select control circuit (68) provides the first pulse width value stored therein to a channel input/output circuit (70). When the second register (66) is written to, the select control circuit (68) provides the second pulse width value stored therein to the channel input/output circuit (70). The select control circuit (68) provides one of the first and second pulse width values such that the signal output by the channel input/output circuit (70) is not erroneous. By writing a new pulse width value to a register associated with an unused channel, the pulse width modulation function is buffered.
摘要翻译：定时器（28）使用两个输出比较定时器通道来形成缓冲的脉冲宽度调制器。提供第一寄存器（62）和第二寄存器以分别存储第一脉冲宽度值和第二寄存器（66）。当第一寄存器（62）被写入时，选择控制电路（68）将存储在其中的第一脉冲宽度值提供给通道输入/输出电路（70）。当第二寄存器（66）被写入时，选择控制电路（68）将存储在其中的第二脉冲宽度值提供给通道输入/输出电路（70）。选择控制电路（68）提供第一和第二脉冲宽度值中的一个，使得由通道输入/输出电路（70）输出的信号不是错误的。通过向与未使用的通道相关联的寄存器写入新的脉冲宽度值，缓冲脉宽调制功能。

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