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    • 5. 发明申请
    • Wafer thickness control during backside grind
    • 背面研磨时的晶片厚度控制
    • US20050158889A1
    • 2005-07-21
    • US11058537
    • 2005-02-15
    • Donald BrouilletteThomas FerenceHarold LindeMichael HibbsRonald Mendelson
    • Donald BrouilletteThomas FerenceHarold LindeMichael HibbsRonald Mendelson
    • H01L21/66H01L21/00H01L21/46
    • H01L22/26
    • A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.
    • 公开了一种用于在背面研磨过程中控制半导体晶片的厚度的方法和装置。 本发明在背面研磨过程中使用晶片厚度的光学测量来确定研磨过程的终点。 优选的方法需要测量透射通过半导体晶片或由半导体晶片反射的光作为入射角或波长的函数。 然后通过使用曲线拟合技术或公式来使用该信息来确定半导体晶片的厚度。 此外,本发明可以用于确定半导体的楔入是否发生,并且如果确实发生楔入,则向间隔设备提供调平信息,使得可以调整研磨表面以减少或消除楔入。
    • 9. 发明申请
    • MASK DEFECT ANALYSIS SYSTEM
    • 掩蔽缺陷分析系统
    • US20070237384A1
    • 2007-10-11
    • US11761856
    • 2007-06-12
    • James BRUCEOrest BULAEdward CONRADWilliam LEIPOLDMichael HIBBSJoshua KRUEGER
    • James BRUCEOrest BULAEdward CONRADWilliam LEIPOLDMichael HIBBSJoshua KRUEGER
    • G06K9/00
    • G03F1/84
    • An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
    • 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合,以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在,位置和类型(透明或不透明)。 最终,根据缺陷是否可能导致产品故障,确定是否废除,修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。