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1. 发明申请

US20180238973A1 MAGNETIC FIELD SENSING APPARATUS AND SENSING METHOD THEREOF 审中-公开
公开(公告)号：US20180238973A1
公开(公告)日：2018-08-23
申请号：US15719586
申请日：2017-09-29
申请人： Fu-Te Yuan , Pei-Chun Kao , Meng-Huang Lai
发明人： Fu-Te Yuan , Pei-Chun Kao , Meng-Huang Lai
IPC分类号： G01R33/09
CPC分类号： G01R33/096
摘要： A magnetic field sensing apparatus and a sensing method are provided. The magnetic field sensing apparatus includes an anisotropic magnetoresistive (AMR) resistor, a current generator, and an arithmetic device. The AMR resistor is configured to provide a first resistance value according to a sensed magnetic field in a first magnetic field sensing phase and provide a second resistance value according to the sensed magnetic field in a second magnetic field sensing phase by a magnetized direction setting operation. The current generator provides a current based on a current direction to flow through two ends of the AMR resistor. The arithmetic device is configured to perform an arithmetic operation with respect to a first voltage difference and a second voltage difference generated according to the current respectively in the first magnetic field sensing phase and the second magnetic field sensing phase, and generate a magnetic field sensing voltage result accordingly.

2. 发明授权

US08462554B2 Over-erase verification and repair methods for flash memory 有权
标题翻译：闪存的过度擦除验证和修复方法
公开(公告)号：US08462554B2
公开(公告)日：2013-06-11
申请号：US13039692
申请日：2011-03-03
申请人： Chung-Meng Huang , Im-Cheol Ha
发明人： Chung-Meng Huang , Im-Cheol Ha
IPC分类号： G11C16/06 , G11C16/28
CPC分类号： G11C16/28 , G11C16/3409 , G11C16/3445
摘要： Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.
摘要翻译：闪存的擦除验证和修复方法。闪存是NOR型堆栈闪存。所公开的方法在逐列的NOR型堆栈闪存的扇区上执行过擦除的列校验测试。在不通过超过列验证测试的列上单独执行超擦除色谱柱修复过程。对于由过度删除的列修复进程处理的列，但是仍然不能通过过擦除的列校验测试，对其每个位执行过擦除位验证测试。无法通过过擦除位验证测试的位进一步通过过度擦除的修复过程单独进行处理。

3. 发明授权

US08164112B2 Electostatic discharge protection circuit coupled on I/O pad 有权
标题翻译：静电放电保护电路耦合在I / O焊盘上
公开(公告)号：US08164112B2
公开(公告)日：2012-04-24
申请号：US09801350
申请日：2001-03-07
申请人： Chun-Hsiang Lai , Meng Huang Liu , Tao Cheng Lu
发明人： Chun-Hsiang Lai , Meng Huang Liu , Tao Cheng Lu
IPC分类号： H01L29/74 , H01L23/62 , H02H9/00
CPC分类号： H01L27/0251 , H01L29/87
摘要： An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.
摘要翻译： I / O焊盘ESD保护电路由SCR电路，第一二极管，第二二极管和防闩锁电路组成。 SCR电路具有分别耦合到I / O焊盘和接地电压的第一连接端子和第二连接端子，以便放电静电电荷。防闩锁电路具有分别耦合到电压源和接地电压的两个端子，以及用于向SCR发送防闩锁信号以用于改变激活速率的另一个连接端子。避免了闩锁现象。

4. 发明授权

US08138276B2 Silicone containing encapsulant 失效
标题翻译：含硅胶囊
公开(公告)号：US08138276B2
公开(公告)日：2012-03-20
申请号：US12591860
申请日：2009-12-03
申请人： Tsung-Yi Chao , Wen-Jeng Lee , Der-Gun Chou , Yen-Cheng Li , Meng-Huang Yan
发明人： Tsung-Yi Chao , Wen-Jeng Lee , Der-Gun Chou , Yen-Cheng Li , Meng-Huang Yan
IPC分类号： C08L63/00 , C08L83/04 , C08L83/12 , H01L23/29
CPC分类号： C08L63/00 , C08G59/4215 , C08G77/14 , C08K5/3475 , C08K5/3492 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a silicone containing encapsulant composition. One embodiment of the encapsulant composition comprises (a) 30˜60 weight % of an epoxy resin; (b) 30˜60 weight % of an acid anhydride curing agent; (c) 0.1˜30 weight % of a Carbinol function silicone resin which can form a homogeneous mixture with (a) and (b) described above; and (d) 0.1˜5 weight % of a reactive UV absorber or HALS; and reactive anti-oxidant and/or phosphor containing flame retardant. The encapsulant composition can be used for a solid state light emitting device to achieve low internal stress and better -anti-yellowing performance.
摘要翻译：本发明涉及含硅氧烷的密封剂组合物。密封剂组合物的一个实施方案包括（a）30〜60重量％的环氧树脂; （b）30〜60重量％的酸酐固化剂; （c）0.1〜30重量％的可与上述（a）和（b）形成均匀混合物的甲醇官能硅氧烷树脂; 和（d）0.1〜5重量％的反应性紫外线吸收剂或HALS; 和反应性抗氧化剂和/或含阻燃剂的磷光体。密封剂组合物可以用于固态发光器件以实现低内应力和更好的防黄变性能。

5. 发明授权

US07882355B2 Encryption/decryption methods and devices utilizing the same 有权
标题翻译：加密/解密方法和利用其的设备
公开(公告)号：US07882355B2
公开(公告)日：2011-02-01
申请号：US11167853
申请日：2005-06-27
申请人： Haw-Kuen Su , Pei-Chieh Hu , Meng-Huang Chu
发明人： Haw-Kuen Su , Pei-Chieh Hu , Meng-Huang Chu
IPC分类号： H04L29/06 , H04K1/00 , G06F11/30 , G11C29/00 , H04L9/00 , G11C11/34 , H04L9/28 , G06F21/00
CPC分类号： G06F12/1408 , G06F21/79 , G06F2221/2107
摘要： An encryption/decryption method and devices for protecting data in a memory device from unauthorized access is provided. First, obtaining a specific code from a memory device and then encrypting the specific code and original data for obtaining encrypted data during a write cycle. Finally, writing the encrypted data to the memory device according to an access address. The access address can be also encrypted to generate the encrypted data. The encryption level increases by this way so that the valuable information is under protection.
摘要翻译：提供了加密/解密方法和用于保护存储器装置中的数据免于未授权访问的装置。首先，从存储器件获得特定代码，然后在写入周期期间加密特定代码和原始数据以获得加密数据。最后，根据访问地址将加密的数据写入存储设备。访问地址也可以被加密以生成加密数据。加密级别以这种方式增加，以便有价值的信息得到保护。

6. 发明申请

US20090179887A1 Digital photo frame with a power saving function and a power saving method thereof 审中-公开
标题翻译：具有省电功能的数码相框及其省电方法
公开(公告)号：US20090179887A1
公开(公告)日：2009-07-16
申请号：US12073718
申请日：2008-03-10
申请人： Chi-Tung Chang , Jar-Haw Lee , Chuan-Ching Tsai , Meng-Huang Chu
发明人： Chi-Tung Chang , Jar-Haw Lee , Chuan-Ching Tsai , Meng-Huang Chu
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G06F3/14 , G09G2330/021 , G09G2330/022 , G09G2360/144
摘要： A digital photo frame with a power saving function includes a time-counting unit, a sensing unit, a displaying unit, and a processing unit. The time-counting unit is used for generating a time-counting signal. The sensing unit is used for sensing the environmental status and generating a sensing signal. The displaying unit is used for displaying an image data. The processing unit controls the sensing unit and the displaying unit. The processing unit further uses a power control unit to control the power supply according to the time-counting signal and the sensing signal so that the digital photo frame operates in a normal mode. After the processing unit does not receive the sensing signal within a pre-determined period counted by the time-counting signal, the processing unit controls the power supply so that the digital photo frame operates in a power saving mode. Hereby, the goal of power saving is achieved.
摘要翻译：具有省电功能的数码相框包括计时单元，感测单元，显示单元和处理单元。时间计数单元用于产生计时信号。感测单元用于感测环境状态并产生感测信号。显示单元用于显示图像数据。处理单元控制感测单元和显示单元。处理单元还使用功率控制单元根据时间计数信号和感测信号来控制电源，使得数字相框以正常模式操作。在处理单元在由计时信号计数的预定时段内没有接收到感测信号之后，处理单元控制电源，使得数字相框以省电模式工作。因此，实现节电的目标。

7. 发明申请

US20060031687A1 Encryption/decryption methods and devices utilizing the same 有权
标题翻译：加密/解密方法和利用其的设备
公开(公告)号：US20060031687A1
公开(公告)日：2006-02-09
申请号：US11167853
申请日：2005-06-27
申请人： Haw-Kuen Su , Pei-Chieh Hu , Meng-Huang Chu
发明人： Haw-Kuen Su , Pei-Chieh Hu , Meng-Huang Chu
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/79 , G06F2221/2107
摘要： An encryption/decryption method and devices for protecting data in a memory device from unauthorized access is provided. First, obtaining a specific code from a memory device and then encrypting the specific code and original data for obtaining encrypted data during a write cycle. Finally, writing the encrypted data to the memory device according to an access address. The access address can be also encrypted to generate the encrypted data. The encryption level increases by this way so that the valuable information is under protection.
摘要翻译：提供了加密/解密方法和用于保护存储器装置中的数据免于未授权访问的装置。首先，从存储器件获得特定代码，然后在写入周期期间加密特定代码和原始数据以获得加密数据。最后，根据访问地址将加密的数据写入存储设备。访问地址也可以被加密以生成加密数据。加密级别以这种方式增加，以便有价值的信息得到保护。

8. 发明授权

US06947267B2 RC controlled ESD circuits for mixed-voltage interface 有权
标题翻译： RC控制ESD电路用于混合电压接口
公开(公告)号：US06947267B2
公开(公告)日：2005-09-20
申请号：US09853591
申请日：2001-05-14
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L27/0292 , H01L27/0285
摘要： The present invention relates an electrostatic discharge (ESD) protection device that is applied to a mixed voltage circuit assembly. The device comprises a RC controlled circuit subassembly and a field transistor, which the RC controlled circuit is coupled with the mixed voltage circuit assembly to substantially control the ESD protection device to be ON or OFF. The field transistor is coupled between a first power supply and a second power supply of said mixed voltage circuit assembly, which is off on the condition of a normal operating condition and is conducting as an ESD event occurred.
摘要翻译：本发明涉及一种应用于混合电压电路组件的静电放电（ESD）保护装置。该装置包括RC控制电路子组件和场晶体管，RC控制电路与混合电压电路组件耦合，以基本上控制ESD保护装置的导通或截止。场晶体管耦合在所述混合电压电路组件的第一电源和第二电源之间，所述第二电源在正常工作条件下处于关断状态，并且当ESD事件发生时导通。

9. 发明授权

US06933540B2 ESD protection apparatus and method for dual-polarity input pad 有权
标题翻译：用于双极性输入板的ESD保护装置和方法
公开(公告)号：US06933540B2
公开(公告)日：2005-08-23
申请号：US10606922
申请日：2003-06-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
IPC分类号： H01L27/02 , H01L29/72
CPC分类号： H01L27/0262 , H01L29/87
摘要： An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.
摘要翻译：用于双极性输入焊盘的ESD保护装置包括形成有第一，第二和第三区域以形成SCR结构的三阱。在第一区域上形成有相反导电类型的第一和第二接地连接区域，在第三区域中形成相反导电类型的第一和第二输入连接区域，跨越第二区域形成桥接区域并延伸到第一和第三区域。在正常操作下，第一，第二和第三区域形成两个背对背二极管。在正极性ESD事件下，在桥与第一区之间发生击穿，从而触发用于正极性ESD保护的SCR电路。在负极性ESD事件下，桥和第三区之间发生击穿，从而触发用于负极性ESD保护的SCR电路。

10. 发明申请

US20050032308A1 Multi-bit vertical memory cell and method of fabricating the same 审中-公开
标题翻译：多位垂直存储单元及其制造方法
公开(公告)号：US20050032308A1
公开(公告)日：2005-02-10
申请号：US10775307
申请日：2004-02-10
申请人： Ching-Nan Hsiao , Chao-Sung Lai , Yung-Meng Huang
发明人： Ching-Nan Hsiao , Chao-Sung Lai , Yung-Meng Huang
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： A multi-bit vertical memory cell and method of fabricating the same. The multi-bit vertical memory cell comprises a semiconductor substrate with a trench, a plurality of bit lines formed therein near its surface and the bottom trench respectively, a plurality of bit line insulating layers over each bit line, a silicon rich oxide layer conformably formed on the sidewall of the trench and the surface of the surface of the bit line insulating layer, and a word line over the silicon rich oxide layer, and the trench is filled with the word line.
摘要翻译：一种多位垂直存储单元及其制造方法。多位垂直存储单元包括具有沟槽的半导体衬底，分别在其表面附近形成的多个位线和底部沟槽，每个位线上的多个位线绝缘层，顺应地形成的富硅氧化物层在沟槽的侧壁和位线绝缘层的表面的表面以及位于富硅氧化物层上的字线，并且沟槽被字线填充。

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