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1. 发明授权

US08462554B2 Over-erase verification and repair methods for flash memory 有权
标题翻译：闪存的过度擦除验证和修复方法
公开(公告)号：US08462554B2
公开(公告)日：2013-06-11
申请号：US13039692
申请日：2011-03-03
申请人： Chung-Meng Huang , Im-Cheol Ha
发明人： Chung-Meng Huang , Im-Cheol Ha
IPC分类号： G11C16/06 , G11C16/28
CPC分类号： G11C16/28 , G11C16/3409 , G11C16/3445
摘要： Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.
摘要翻译：闪存的擦除验证和修复方法。闪存是NOR型堆栈闪存。所公开的方法在逐列的NOR型堆栈闪存的扇区上执行过擦除的列校验测试。在不通过超过列验证测试的列上单独执行超擦除色谱柱修复过程。对于由过度删除的列修复进程处理的列，但是仍然不能通过过擦除的列校验测试，对其每个位执行过擦除位验证测试。无法通过过擦除位验证测试的位进一步通过过度擦除的修复过程单独进行处理。

2. 发明授权

US06518828B2 Pumping voltage regulation circuit 有权
公开(公告)号：US06518828B2
公开(公告)日：2003-02-11
申请号：US10013529
申请日：2001-12-13
申请人： Sung-Whan Seo , Im-Cheol Ha
发明人： Sung-Whan Seo , Im-Cheol Ha
IPC分类号： H03K301
CPC分类号： H02M3/073
摘要： A pumping voltage regulation circuit adjusts a pumping voltage to maintain a preset voltage level regardless of the variation of a supply voltage. The pumping voltage regulation circuit includes a clock adjusting unit for producing a second clock signal according to a combination of a first clock signal and a first control signal or that of the first clock signal and a second control signal, a pumping voltage generating unit for producing a pumping voltage in response to the second clock signal outputted from the clock adjusting unit, a diode chain for dividing the pumping voltage and a sense amplifier for outputting the second control signal by comparing an output voltage of the diode chain with a reference voltage.

3. 发明授权

US06377496B1 Word line voltage regulation circuit 有权
标题翻译：字线电压调节电路
公开(公告)号：US06377496B1
公开(公告)日：2002-04-23
申请号：US09722490
申请日：2000-11-28
申请人： Poong Yeub Lee , Im Cheol Ha , Kye Wan Shin , Oh Won Kwon , Sung Hwan Seo
发明人： Poong Yeub Lee , Im Cheol Ha , Kye Wan Shin , Oh Won Kwon , Sung Hwan Seo
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C8/08 , G11C16/08
摘要： A word line voltage regulation circuit includes a first comparator for comparing a first reference voltage and the potential of an output node; a first switching element for supplying the supply voltage to the output node depending on the output signal of the first comparator; a second comparator for comparing a second reference voltage and the potential of the output node; a second switching element for regulating the potential of the output node depending on the output signal of the second comparator; a third switching element for transmitting the potential of the output node to a decoder circuit depending on a first control signal; and a fourth switching element for supplying the supply voltage to the decoder circuit depending on a second control signal.
摘要翻译：字线电压调节电路包括用于比较第一参考电压和输出节点的电位的第一比较器; 第一开关元件，用于根据第一比较器的输出信号将输出电压提供给输出节点; 用于比较第二参考电压和输出节点的电位的第二比较器; 第二开关元件，用于根据第二比较器的输出信号调节输出节点的电位; 第三开关元件，用于根据第一控制信号将输出节点的电位传输到解码器电路; 以及第四开关元件，用于根据第二控制信号向解码器电路提供电源电压。

4. 发明申请

US20120224432A1 OVER-ERASE VERIFICATION AND REPAIR METHODS FOR FLASH MEMORY 有权
标题翻译： FLASH存储器的过滤验证和修复方法
公开(公告)号：US20120224432A1
公开(公告)日：2012-09-06
申请号：US13039692
申请日：2011-03-03
申请人： Chung-Meng Huang , Im-Cheol Ha
发明人： Chung-Meng Huang , Im-Cheol Ha
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/3409 , G11C16/3445
摘要： Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.
摘要翻译：闪存的擦除验证和修复方法。闪存是NOR型堆栈闪存。所公开的方法在逐列的NOR型堆栈闪存的扇区上执行过擦除的列校验测试。在不通过超过列验证测试的列上单独执行超擦除色谱柱修复过程。对于由过度删除的列修复进程处理的列，但是仍然不能通过过擦除的列校验测试，对其每个位执行过擦除位验证测试。无法通过过擦除位验证测试的位进一步通过过度擦除的修复过程单独进行处理。

5. 发明授权

US6064623A Row decoder having global and local decoders in flash memory devices 有权
标题翻译：行解码器在闪存设备中具有全局和本地解码器
公开(公告)号：US6064623A
公开(公告)日：2000-05-16
申请号：US223384
申请日：1998-12-30
申请人： Im Cheol Ha
发明人： Im Cheol Ha
IPC分类号： G11C16/06 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： The present invention relates to a row decoder in a flash memory device; and, more particularly, to a row decoder having global and local row decoders to reduce a loading of the high voltage and a chip area. The row decoder according to the present invention comprises a plurality of global row decoders for generating a first control signal and a second control signal according to an operation mode of the flash memory, wherein each global row decoder produces a first voltage level from a first power supply and a second voltage level from a second power supply, which respectively correspond to the first and second control signals, in response to first and second addresses from a predecoder; and a plurality of local row decoders for selecting a word line selection signal in response to the first and second control signals, wherein each local row decoder produces a third voltage level from a third power supply and a fourth voltage level from a fourth power supply which receives a third address from the predecoder and wherein the first control signal is out of phase from the second control signal.
摘要翻译：本发明涉及一种闪存装置中的行解码器; 更具体地，涉及具有全局和局部行解码器的行解码器，以减少高电压和芯片面积的负载。根据本发明的行解码器包括多个全局行解码器，用于根据闪存的操作模式产生第一控制信号和第二控制信号，其中每个全局行解码器从第一电源产生第一电压电平响应来自预解码器的第一和第二地址，从第二电源供应和分别对应于第一和第二控制信号的第二电压电平; 以及多个本地行解码器，用于响应于第一和第二控制信号来选择字线选择信号，其中每个本地行解码器从第三电源产生第三电压电平，并从第四电源产生第四电压电平，从所述预解码器接收第三地址，并且其中所述第一控制信号与所述第二控制信号异相。

6. 发明授权

US06870769B1 Decoder circuit used in a flash memory device 失效
标题翻译：解码器电路用于闪存设备
公开(公告)号：US06870769B1
公开(公告)日：2005-03-22
申请号：US08998157
申请日：1997-12-24
申请人： Im Cheol Ha
发明人： Im Cheol Ha
IPC分类号： G11C16/06 , G11C8/08 , G11C16/00 , G11C16/04 , G11C16/08
CPC分类号： G11C8/08 , G11C16/08
摘要： A decoder circuit according to the present invention comprises a global row decoder consisted of a first decoding means selected according to a row address signal and a second decoding means to which an output signal of the first decoding means and an erasure signal are input and a local row decoder for selecting each global word line signal outputted from the global row decoder. The local row decoder is consisted of a first and second transistors to the word line signal is input, and a third, fourth and fifth transistors outputting a first voltage supply signal and a second voltage supply signal to a sector word line.
摘要翻译：根据本发明的解码器电路包括：全局行解码器，由根据行地址信号选择的第一解码装置和第一解码装置的输出信号和擦除信号输入的第二解码装置组成，行解码器，用于选择从全局行解码器输出的每个全局字线信号。本地行解码器由输入字线信号的第一和第二晶体管组成，第三，第四和第五晶体管将第一电压供应信号和第二电压供应信号输出到扇区字线。

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