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1. 发明申请

US20150121325A1 SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE AGAINST ONE OR MORE VIOLATION RULES 有权
标题翻译：用于测试对一个或多个违反规则的设备进行仿真的模拟系统和方法
公开(公告)号：US20150121325A1
公开(公告)日：2015-04-30
申请号：US14398901
申请日：2012-05-31
申请人： Xavier Hours , Pascal Caunegre , Christophe Oger , Mehul Shroff
发明人： Xavier Hours , Pascal Caunegre , Christophe Oger , Mehul Shroff
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F11/261 , G06F17/5022 , G06F17/5045 , G06F17/5081
摘要： A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation. The simulation system further comprises a reporting unit for preparing a report of the rule scores associated with the one or more violation rules and for reporting the report to a user. A method of testing a simulation of a device against one or more violation rules is described.
摘要翻译：描述了用于针对一个或多个违规规则来测试设备的模拟的仿真系统。该仿真系统包括：用于使用设备设计，设备模型和仿真场景执行设备的仿真的设备模拟器; 和一个或多个违规监视器，每个违规规则一个。每个违规监视器包括违反信息检测器，用于在执行模拟期间检测一个或多个违反相应违规规则的违规，并且对于每个违规，确定表示相应违规的信息; 侵权分数单元，用于针对每个违反相应的违规规则的违反分数，根据表示违规的信息和违规规则特定方案来计算违规分数，以及规则评分单元，用于根据相应的违规规则，来自模拟期间一次或多次违规的违规分数的规则得分。所述模拟系统还包括报告单元，用于准备与所述一个或多个违规规则相关联的所述规则得分的报告，以及用于向所述用户报告所述报告。描述了针对一个或多个违规规则来测试设备的仿真的方法。

2. 发明申请

US20130305202A1 MISMATCH VERIFICATION DEVICE AND METHODS THEREOF 有权
标题翻译：误码校验装置及其方法
公开(公告)号：US20130305202A1
公开(公告)日：2013-11-14
申请号：US13466642
申请日：2012-05-08
申请人： Mehul Shroff , Sanjay R. Parihar , Edward O. Travis
发明人： Mehul Shroff , Sanjay R. Parihar , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.
摘要翻译：方法可以包括识别包括设备的第一和第二实例化的设备设计，识别设备设计的层，基于第一实例的层识别第一实例化的设备设计的第一区域，以及第二区域基于第二实例化层的第二实例化设备设计。识别所述设备设计的第一比较层，其包括多个第一比较特征，所述第一比较特征包括所述第一区域内的第一比较特征和所述第二区域内的第二比较特征，确定所述第一比较特征与所述第二比较特征之间的差，以及确定所述差是否满足公差以确定所述第一实例是否与所述第二实例化匹配。

3. 发明申请

US20070207404A1 Treatment for reduction of line edge roughness 失效
标题翻译：减少线边缘粗糙度的处理
公开(公告)号：US20070207404A1
公开(公告)日：2007-09-06
申请号：US11369513
申请日：2006-03-06
申请人： Jinmiao Shen , Jonathan Cobb , William Darlington , Brian Fisher , Mark Hall , Vikas Sheth , Mehul Shroff , James Vasek
发明人： Jinmiao Shen , Jonathan Cobb , William Darlington , Brian Fisher , Mark Hall , Vikas Sheth , Mehul Shroff , James Vasek
IPC分类号： G03C1/00
CPC分类号： G03F7/168
摘要： A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
摘要翻译：提供了一种降低光致抗蚀剂层中的线边缘粗糙度（LER）的方法。根据该方法，将一层光致抗蚀剂施加到基底上。然后在包括选自氢，氮和含氟材料的至少一种气体的气氛中对光致抗蚀剂层进行构图和退火。优选地，在图案化光致抗蚀剂之后进行退火，但是在修剪之后或之后。

4. 发明申请

US20070173004A1 EPI T-gate structure for CoSi2 extendibility 有权
标题翻译： EPI T-gate结构，CoSi2可扩展性
公开(公告)号：US20070173004A1
公开(公告)日：2007-07-26
申请号：US11340049
申请日：2006-01-26
申请人： Mark Hall , Dharmesh Jawarani , Mehul Shroff , Edward Travis
发明人： Mark Hall , Dharmesh Jawarani , Mehul Shroff , Edward Travis
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的顶部临界尺寸（例如，40nm以上），使得硅化物可以至少在T形的上部区域（90）中由第一材料（例如CoSi 2 N 2）形成结构（96），而不会导致由于在较小临界尺寸下某些硅化物可能发生的团聚和排空引起的增加的电阻。

5. 发明申请

US20070134921A1 Method of forming a semiconductor device having dummy features 有权
标题翻译：形成具有虚拟特征的半导体器件的方法
公开(公告)号：US20070134921A1
公开(公告)日：2007-06-14
申请号：US11302769
申请日：2005-12-14
申请人： Ruiqi Tian , Willard Conley , Mehul Shroff
发明人： Ruiqi Tian , Willard Conley , Mehul Shroff
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0334 , H01L21/31053 , H01L21/311 , H01L21/3213 , H01L21/32139 , Y10S438/926
摘要： A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.
摘要翻译：一种用于形成半导体器件的方法包括在布局中提供多个特征，从多个特征中选择关键特征，将布置中的第一多个短距离虚拟蚀刻特征放置在离关键特征的第一距离处以增加临界特征附近的特征密度，其中第一多个短距离虚拟蚀刻特征中的每一个具有第一宽度，从布局去除第一多个短程虚拟蚀刻特征中的至少一个，随后将干扰至少一个有源特征的电性能，使得第二多个短距离虚拟蚀刻特征保留，并且使用布局来在半导体衬底上图案化。

6. 发明申请

US20070196988A1 Poly pre-doping anneals for improved gate profiles 审中-公开
标题翻译：聚预掺杂退火以改善浇口型材
公开(公告)号：US20070196988A1
公开(公告)日：2007-08-23
申请号：US11360796
申请日：2006-02-23
申请人： Mehul Shroff , Mark Hall , Paul Grudowski , Tab Stephens , Phillip Stout , Olubunmi Adetutu
发明人： Mehul Shroff , Mark Hall , Paul Grudowski , Tab Stephens , Phillip Stout , Olubunmi Adetutu
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/28123 , H01L21/32155 , H01L21/823437 , H01L21/823828
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.
摘要翻译：半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的栅极堆叠（32），从而通过注入栅叠层而形成具有垂直侧壁轮廓的蚀刻栅极（92,94）（32）和氮（42）和掺杂剂（52），然后使用快速热退火（62）在选定的温度下加热多晶硅栅极堆叠（32）以退火氮和掺杂剂，从而随后蚀刻多晶硅栅极堆叠（32）产生具有更理想化的垂直栅极侧壁轮廓的蚀刻栅极（92,94）。

7. 发明申请

US20070194392A1 Method and apparatus for indicating directionality in integrated circuit manufacturing 有权
标题翻译：用于指示集成电路制造中的方向性的方法和装置
公开(公告)号：US20070194392A1
公开(公告)日：2007-08-23
申请号：US11360925
申请日：2006-02-23
申请人： Edward Travis , Mehul Shroff , Donald Smeltzer , Traci Smith
发明人： Edward Travis , Mehul Shroff , Donald Smeltzer , Traci Smith
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L23/544 , H01L22/34 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
摘要翻译：集成电路包括形成为集成电路的一部分的视觉辨别指示，以指示集成电路的非视觉辨别特性的方向性。

8. 发明申请

US20060105568A1 Plasma treatment for surface of semiconductor device 失效
标题翻译：半导体器件表面等离子体处理
公开(公告)号：US20060105568A1
公开(公告)日：2006-05-18
申请号：US10987790
申请日：2004-11-12
申请人： Jin Shen , Brian Fisher , Mark Hall , Kurt Junker , Vikas Sheth , Mehul Shroff
发明人： Jin Shen , Brian Fisher , Mark Hall , Kurt Junker , Vikas Sheth , Mehul Shroff
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/02164 , H01L21/02274 , H01L21/0234 , H01L21/0276 , H01L21/3105 , H01L21/31612
摘要： A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.
摘要翻译：一种用于形成半导体器件（10）的方法包括在半导体器件（10）上形成有机抗反射涂层（OARC）层（18）。在OARC层（18）上形成四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在至多约300摄氏度的温度下暴露于基于氧的等离子体。在替代实施例中，首先将TEOS层（20）暴露于基于氧的等离子体之前的氮基等离子体。光致抗蚀剂层（22）形成在TEOS层（20）上并被图案化。在施加光致抗蚀剂之前，通过将氧基等离子体和氮基等离子体施加到TEOS层（20）上，减少了图案缺陷。

9. 发明授权

US06583043B2 Dielectric between metal structures and method therefor 有权
公开(公告)号：US06583043B2
公开(公告)日：2003-06-24
申请号：US09918429
申请日：2001-07-27
申请人： Mehul Shroff , Gerald G. Benard , Philip Grigg
发明人： Mehul Shroff , Gerald G. Benard , Philip Grigg
IPC分类号： H01L2144
CPC分类号： H01L21/76885 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Two conductors of the same layer are separated by a low-K dielectric to minimize capacitance between them. The first and second conductors may have sidewalls with conductive barriers. The conductive barriers are separated from the low-K dielectric by spacers. The dielectric spacers have a top portion and a lower portion in which the top portion may have a higher dielectric constant than the lower portion or may be the same material. The two conductors are formed in trenches in a convenient dielectric. Prior to forming the conductors, the conductive barriers are deposited in the trench. After the conductors are formed, the convenient dielectric is removed. The dielectric spacers are formed adjacent to the conductive barriers. The low-K dielectric is then deposited adjacent to the dielectric spacers and not in contact with the conductive barriers.

10. 发明授权

US10041993B2 Safe operating area checking method and apparatus 有权
公开(公告)号：US10041993B2
公开(公告)日：2018-08-07
申请号：US14917100
申请日：2013-09-05
申请人： Xavier Hours , Aldric L'Hernault , Christophe Oger , Mehul Shroff
发明人： Xavier Hours , Aldric L'Hernault , Christophe Oger , Mehul Shroff
IPC分类号： G01R31/00 , G01R31/28 , G06F17/50
摘要： The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.

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