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    • 1. 发明授权
    • Loading/discarding acquired data for vector load instruction upon determination of prediction success of multiple preceding branch instructions
    • 在确定多个先前分支指令的预测成功之后,加载/丢弃用于向量加载指令的获取数据
    • US08850167B2
    • 2014-09-30
    • US13240614
    • 2011-09-22
    • Masao Fukagawa
    • Masao Fukagawa
    • G06F9/38G06F17/16G06F9/30
    • G06F9/38G06F9/30036G06F9/30043G06F9/3859G06F17/16
    • Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality of vector data based on the issued vector load instruction from the main memory, a determination unit that determines a success or a failure of the branch target prediction after the branch target is determined, and a vector load management unit that, when the branch target prediction is determined to be a success, acquires all vector data based on the plurality of acquisition requests and then transfers all the vector data to a vector register, and, when the branch target prediction is determined to be a failure, discards the vector data acquired by the issued acquisition requests.
    • 提供了一种处理器,包括:指令发布单元,其基于分支指令中的分支目标的分支目标预测发出从主存储器读取的向量加载指令;数据获取单元,其开始发出多个获取请求, 基于来自主存储器的所发出的矢量加载指令的多个向量数据,确定分支目标确定之后的分支目标预测的成功或失败的确定单元;以及矢量负载管理单元,当分支目标 确定预测成功,基于多个获取请求获取所有矢量数据,然后将所有矢量数据传送到向量寄存器,并且当分支目标预测被确定为故障时,丢弃所获取的矢量数据 由发出的收购要求。
    • 2. 发明申请
    • PROCESSOR AND VECTOR LOAD INSTRUCTION EXECUTION METHOD
    • 处理器和矢量负载指令执行方法
    • US20120089824A1
    • 2012-04-12
    • US13240614
    • 2011-09-22
    • MASAO FUKAGAWA
    • MASAO FUKAGAWA
    • G06F9/38
    • G06F9/38G06F9/30036G06F9/30043G06F9/3859G06F17/16
    • Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality of vector data based on the issued vector load instruction from the main memory, a determination unit that determines a success or a failure of the branch target prediction after the branch target is determined, and a vector load management unit that, when the branch target prediction is determined to be a success, acquires all vector data based on the plurality of acquisition requests and then transfers all the vector data to a vector register, and, when the branch target prediction is determined to be a failure, discards the vector data acquired by the issued acquisition requests.
    • 提供了一种处理器,包括:指令发布单元,其基于分支指令中的分支目标的分支目标预测发出从主存储器读取的向量加载指令;数据获取单元,其开始发出多个获取请求, 基于来自主存储器的所发出的矢量加载指令的多个向量数据,确定分支目标确定之后的分支目标预测的成功或失败的确定单元;以及矢量负载管理单元,当分支目标 确定预测成功,基于多个获取请求获取所有矢量数据,然后将所有矢量数据传送到向量寄存器,并且当分支目标预测被确定为故障时,丢弃所获取的矢量数据 由发出的收购要求。
    • 5. 发明授权
    • Processor for managing latest speculation states and efficiently reusing reorder buffer entries
    • 用于管理最新投机状态的处理器,并有效地重用重新排序缓冲区条目
    • US06938150B2
    • 2005-08-30
    • US10040392
    • 2002-01-09
    • Masao Fukagawa
    • Masao Fukagawa
    • G06F9/38G06F9/00
    • G06F9/3836G06F9/3838G06F9/384G06F9/3842G06F9/3855G06F9/3861
    • By using an entry number (WRB number) of a re-order buffer 6, each of function units such as an operation unit 3, a store unit 4, a load unit 5, etc. notifies to the re-order buffer 6 the processing end for a instruction stored in the entry concerned in the unit thereof. The load unit 5 manages the latest speculation state of a load instruction issued on the basis of a branch prediction success/failure signal output from the branch unit 2, and makes no notification to the re-order buffer 6 on the basis of WRB number for subsequent load instructions of a branch-prediction failed branch instruction even when the processing of the instruction is finished. Accordingly, the re-order buffer 6 can re-use entries in which the subsequent instructions of the branch prediction failed branch instruction are stored.
    • 通过使用重新排序缓冲器6的入口号(WRB号),诸如操作单元3,存储单元4,加载单元5等功能单元中的每个功能单元向重新排序缓冲器6通知处理 结束存储在其单元中的相关条目中的指令。 负载单元5管理基于从分支单元2输出的分支预测成功/失败信号而发出的加载指令的最新推测状态,并且根据WRB号不向重新排序缓冲器6发送通知 即使当指令的处理结束时,分支预测失败分支指令的后续加载指令。 因此,重新排序缓冲器6可以重新使用存储分支预测失败分支指令的后续指令的条目。