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1. 发明授权

US07926478B2 Super abrasive grain wire saw winding structure, super abrasive grain wire saw cutting device, and super abrasive grain wire saw winding method 有权
标题翻译：超级磨粒线绕线结构，超级磨粒锯线切割装置，超细磨料线锯绕线方式
公开(公告)号：US07926478B2
公开(公告)日：2011-04-19
申请号：US10571131
申请日：2004-06-03
申请人： Masanori Nakai , Masaaki Yamanaka , Yoshizumi Ishitobi
发明人： Masanori Nakai , Masaaki Yamanaka , Yoshizumi Ishitobi
IPC分类号： B28D1/06 , B28D1/08 , B24B7/00 , B24B9/00 , B26D5/20
CPC分类号： B65H54/2872 , B23D57/0061 , B23D61/185 , B24B27/0633 , Y10T83/9292
摘要： A superabrasive wire saw-wound structure includes a superabrasive wire saw (10) formed with an average diameter D and a reel (1). The superabrasive wire saw (10) includes a core wire (11), a bonding material (12) surrounding a surface of the core wire (11), and a plurality of superabrasive grains (13) bonded to the surface of the core wire (11) with the bonding material (12). The reel (1) includes a peripheral surface (2) having one end (3) and the other end (4). The superabrasive wire saw (10) which is to be unreeled successively toward a workpiece is wound around the peripheral surface (2) reciprocatingly between the one end (3) and the other end (4) to be multi-layered. A pitch P for winding the superabrasive wire saw (10) around the peripheral surface (2) between the one end (3) and the other end (4) satisfies a relation of D
摘要翻译：超级磨损线锯绕结构包括形成有平均直径D和卷轴（1）的超级磨损线锯（10）。所述超细金属丝锯（10）包括芯线（11），围绕所述芯线（11）的表面的接合材料（12）以及与所述芯线的表面接合的多个超磨粒（13） 11）与接合材料（12）。卷轴（1）包括具有一端（3）和另一端（4）的外周表面（2）。将要向工件连续取出的超级磨料钢丝绳（10）围绕在一端（3）和另一端（4）之间往复运动的外周表面（2）缠绕成多层。围绕一端（3）和另一端（4）之间的周边表面（2）缠绕超级磨料线锯（10）的间距P满足D

2. 发明授权

US4464589A IL Buffer having higher breakdown levels 失效
标题翻译： IL缓冲液具有较高的击穿水平
公开(公告)号：US4464589A
公开(公告)日：1984-08-07
申请号：US405272
申请日：1982-08-04
申请人： Toshinori Moriyasu , Masanori Nakai
发明人： Toshinori Moriyasu , Masanori Nakai
IPC分类号： H01L21/8226 , H01L21/331 , H01L27/082 , H01L29/73 , H03K17/10 , H03K19/018 , H03K19/091 , H03K17/08 , H03K19/003
CPC分类号： H03K19/091 , H03K19/01818
摘要： A buffer circuit is provided wherein bipolar transistors are connected to the output terminal of an IIL gate. The buffer circuit includes an IIL gate having a plurality of output terminals. The output terminals of the IIL gate are respectively connected to the bases of the bipolar transistors of which the emitter-collector paths are connected in series between a buffer output terminal and a reference voltage terminal.
摘要翻译：提供了一种缓冲电路，其中双极晶体管连接到IIL门的输出端。缓冲电路包括具有多个输出端子的IIL门。 IIL栅极的输出端子分别连接到串联在缓冲器输出端子和参考电压端子之间的发射极 - 集电极路径的双极晶体管的基极。

3. 发明授权

US4459606A Integrated injection logic semiconductor devices 失效
标题翻译：集成注入逻辑半导体器件
公开(公告)号：US4459606A
公开(公告)日：1984-07-10
申请号：US644296
申请日：1975-12-24
申请人： Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
发明人： Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L27/02 , H01L29/73 , H01L27/04 , H03K19/091
CPC分类号： H01L27/0214
摘要： The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.
摘要翻译：集成注入逻辑半导体器件包括N型半导体衬底，层叠在N型半导体衬底上的P型半导体层，延伸穿过P型半导体层到达N型半导体衬底的第一N型区域，P型区域形成在第一N型区域中，并且沿着第一N型区域的外周具有周边，以及形成在P型半导体层中的第二N型区域。集成注入逻辑半导体器件分别由利用P型区域，第一N型区域和P型半导体层作为发射极，基极和集电极的PNP横向晶体管构成，以及利用N型半导体的NPN垂直晶体管基板，P型半导体层和第二N型区域分别作为发射极，基极和集电极。

4. 发明授权

US4058419A Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques 失效
标题翻译：使用自对准双扩散技术制造集成注入逻辑半导体器件的方法
公开(公告)号：US4058419A
公开(公告)日：1977-11-15
申请号：US644294
申请日：1975-12-24
申请人： Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
发明人： Yukuya Tokumaru , Masanori Nakai , Satoshi Shinozaki , Junichi Nakamura , Shintaro Ito , Yoshio Nishi
IPC分类号： H01L21/033 , H01L21/8226 , H01L27/02 , H01L21/22 , H01L21/76 , H01L27/04
CPC分类号： H01L21/8226 , H01L21/033 , H01L27/0233
摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.
摘要翻译：通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件晶体管。

5. 发明授权

US08356397B2 Manufacturing method of clutch for automatic transmission and automatic transmission 有权
标题翻译：自动变速器和自动变速箱离合器的制造方法
公开(公告)号：US08356397B2
公开(公告)日：2013-01-22
申请号：US12499571
申请日：2009-07-08
申请人： Hideo Toyota , Naohiro Sakaue , Katsutoshi Mukai , Koichi Matsuura , Shinichiro Tenma , Masashi Morihiro , Jun Nakamura , Masanori Nakai
发明人： Hideo Toyota , Naohiro Sakaue , Katsutoshi Mukai , Koichi Matsuura , Shinichiro Tenma , Masashi Morihiro , Jun Nakamura , Masanori Nakai
IPC分类号： B21D53/28 , B21K1/30 , B23P11/00 , B23P15/14
CPC分类号： F16D25/0638 , F16D21/06 , F16D2021/0661 , F16D2048/0212 , F16D2250/00 , Y10T29/49464 , Y10T29/49826
摘要： In a clutch manufacturing method, inner peripheral portions of drum members, of two clutches are connected to a sleeve member, and a piston, a seal plate and a return spring are provided between the drum members, an insulator to apply electric isolation between the piston and the drum member or between the seal plate and another drum member is attached to either the piston or the seal plate. Then, the drum member, to which the electric isolation with the insulator is not applied, is connected to the sleeve member. Then, the piston, return sprig and seal plate are assembled to the sleeve member to which the drum member has been connected. Finally, the drum member, to which the electric isolation with the insulator has been applied, is connected to the sleeve member with electric welding.
摘要翻译：在离合器制造方法中，两个离合器的鼓构件的内周部分连接到套筒构件，并且活塞，密封板和复位弹簧设置在鼓构件之间，绝缘体用于在活塞之间施加电隔离并且鼓构件或密封板和另一个鼓构件之间安装在活塞或密封板上。然后，与绝缘体电隔离的鼓部件与套筒部件连接。然后，将活塞，返回喷嘴和密封板组装到与鼓构件已经连接的套筒构件上。最后，已经施加了与绝缘体的电隔离的鼓构件通过电焊接连接到套筒构件。

6. 发明申请

US20070023027A1 Super abrasive grain wire saw winding structure, super abrasive grain wire saw cutting device, and super abrasive grain wire saw winding method 有权
标题翻译：超级磨粒线绕线结构，超级磨粒锯线切割装置，超细磨料线锯绕线方式
公开(公告)号：US20070023027A1
公开(公告)日：2007-02-01
申请号：US10571131
申请日：2004-06-03
申请人： Masanori Nakai , Masaaki Yamanaka , Yoshizumi Ishitobi
发明人： Masanori Nakai , Masaaki Yamanaka , Yoshizumi Ishitobi
IPC分类号： B28D1/08
CPC分类号： B65H54/2872 , B23D57/0061 , B23D61/185 , B24B27/0633 , Y10T83/9292
摘要： A superabrasive wire saw-wound structure includes a superabrasive wire saw (10) formed with an average diameter D and a reel (1). The superabrasive wire saw (10) includes a core wire (11), a bonding material (12) surrounding a surface of the core wire (11), and a plurality of superabrasive grains (13) bonded to the surface of the core wire (11) with the bonding material (12). The reel (1) includes a peripheral surface (2) having one end (3) and the other end (4). The superabrasive wire saw (10) which is to be unreeled successively toward a workpiece is wound around the peripheral surface (2) reciprocatingly between the one end (3) and the other end (4) to be multi-layered. A pitch P for winding the superabrasive wire saw (10) around the peripheral surface (2) between the one end (3) and the other end (4) satisfies a relation of D
摘要翻译：超级磨损线锯绕结构包括形成有平均直径D和卷轴（1）的超级磨损线锯（10）。所述超细金属丝锯（10）包括芯线（11），围绕所述芯线（11）的表面的接合材料（12）以及与所述芯线的表面接合的多个超磨粒（13） 11）与接合材料（12）。卷轴（1）包括具有一端（3）和另一端（4）的外周表面（2）。将要向工件连续取出的超级磨料钢丝绳（10）围绕在一端（3）和另一端（4）之间往复运动的外周表面（2）缠绕成多层。围绕一端（3）和另一端（4）之间的周边表面（2）缠绕超级磨料线锯（10）的间距P满足D

7. 发明授权

US4680331A Aqueous coating composition of fluorocarbon resin 失效
标题翻译：氟碳树脂的水性涂料组合物
公开(公告)号：US4680331A
公开(公告)日：1987-07-14
申请号：US832622
申请日：1986-02-25
申请人： Takeshi Suzuki , Shigetake Tominaga , Masanori Nakai
发明人： Takeshi Suzuki , Shigetake Tominaga , Masanori Nakai
IPC分类号： C08J7/04 , C08L27/12 , C08L83/04 , C09D127/12 , C09D127/16 , C08K5/54
CPC分类号： C09D127/12 , C08L83/04
摘要： This invention provides a fluorocarbon resin aqueous coating composition comprising:(a) a fluorocarbon resin, and based on the amount by weight of the resin(b) about 1 to about 10% by weight of a silicone emulsion (calculated as silicone oil contained),(c) about 1 to about 40% by weight of a flaky inorganic material, and(d) about 3 to about 10% by weight of a nonionic surfactant, or a mixture of nonionic surfactant and anionic surfactant,the composition containing about 25 to about 75% by weight of water based on the whole composition.
摘要翻译：本发明提供了一种氟碳树脂水性涂料组合物，其包含：（a）氟碳树脂，并且基于树脂（b）的重量比为约1至约10重量％的硅氧烷乳液（以含硅油计算），（c）约1至约40重量％的片状无机材料，和（d）约3至约10重量％的非离子表面活性剂，或非离子表面活性剂和阴离子表面活性剂的混合物，所述组合物含有约25 至约75重量％的水。

8. 发明授权

US4489247A Integrated injection logic circuit with test pads on injector common line 失效
标题翻译：集成注入逻辑电路，带有喷射器公共线上的测试垫
公开(公告)号：US4489247A
公开(公告)日：1984-12-18
申请号：US349207
申请日：1982-02-17
申请人： Masashi Ikeda , Yukuya Tokumaru , Masanori Nakai , Masaki Ota
发明人： Masashi Ikeda , Yukuya Tokumaru , Masanori Nakai , Masaki Ota
IPC分类号： H01L27/082 , G01R31/317 , H01L21/8226 , H01L27/02 , H03K19/091 , G01R19/00 , H01L27/10 , H01L29/70
CPC分类号： G01R31/31715 , G01R31/317 , G01R31/31712 , H01L27/0233
摘要： An integrated injection logic circuit includes a plurality of integrated injection logic gates each having a PNP transistor for injector and NPN transistor for signal inversion, and an injector common line to which the respective injector PNP transistors are commonly connected. A test pad for electric probing is provided at least one location of the injector common line.
摘要翻译：集成注入逻辑电路包括多个集成注入逻辑门，每个具有用于注入的PNP晶体管和用于信号反相的NPN晶体管，以及各个注入PNP晶体管共同连接的注入器公共线。用于电探测的测试垫设置在喷射器公共管线的至少一个位置。

9. 发明授权

US4470061A Integrated injection logic 失效
标题翻译：集成注入逻辑
公开(公告)号：US4470061A
公开(公告)日：1984-09-04
申请号：US336275
申请日：1981-12-31
申请人： Masanori Nakai
发明人： Masanori Nakai
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L27/02 , H01L29/73 , H03K17/04 , H03K19/013 , H03K19/018 , H03K19/091 , H01L27/04
CPC分类号： H01L27/0233 , H03K19/091 , Y10S257/914
摘要： An integrated injection logic having a first semiconductor region of first conductivity type, a second semiconductor region of second conductivity type formed in the first semiconductor region, a plurality of third semiconductor regions of first conductivity type formed in the second semiconductor region, and a fourth semiconductor region of second conductivity type formed in the first semiconductor region. A fifth semiconductor region of second conductivity type is formed in the first semiconductor region and in the vicinity of the second semiconductor region and is connected to one of the plurality of third semiconductor regions in order to eliminate minority carriers stored in the first semiconductor region and the second semiconductor region.
摘要翻译：一种具有第一导电类型的第一半导体区域，形成在第一半导体区域中的第二导电类型的第二半导体区域，形成在第二半导体区域中的多个第一导电类型的第三半导体区域和第四半导体区域的集成注入逻辑形成在第一半导体区域中的第二导电类型的区域。第二导电类型的第五半导体区域形成在第一半导体区域中并且在第二半导体区域附近并且连接到多个第三半导体区域中的一个，以消除存储在第一半导体区域中的少数载流子，并且第二半导体区域。

10. 发明授权

US4260906A Semiconductor device and logic circuit constituted by the semiconductor device 失效
标题翻译：由半导体器件构成的半导体器件和逻辑电路
公开(公告)号：US4260906A
公开(公告)日：1981-04-07
申请号：US906021
申请日：1978-05-15
申请人： Yukuya Tokumaru , Masanori Nakai
发明人： Yukuya Tokumaru , Masanori Nakai
IPC分类号： H01L27/02 , H03K19/084 , H03K19/091 , H01L27/04
CPC分类号： H03K19/084 , H01L27/0237 , H03K19/091 , Y10S148/087 , Y10S148/088 , Y10S148/139
摘要： A semiconductor device comprises a P type semiconductor substrate; an N type layer buried in the P type substrate; and an N type isolating region extending from the surface of the P type substrate to the N type buried region to provide a P type isolated region in the P type substrate. In the P type isolated region marked off by the N type isolating region is formed a first N type region so as not to contact the N type isolating region and buried region and a P type second region is diffused in the first N type region. A logic circuit is constituted by a first vertical PNP transistor formed of the P type second region, first N type region and P type isolated region and a second vertical NPN transistor formed of the first N type region, P type isolated region and N type buried region.
摘要翻译：半导体器件包括P型半导体衬底; 埋在P型衬底中的N型层; 以及从P型基板的表面延伸到N型掩埋区域的N型绝缘区域，以在P型基板中提供P型隔离区域。在由N型隔离区域标记的P型隔离区域中形成第一N型区域，以便不与N型隔离区域和掩埋区域接触，并且P型第二区域在第一N型区域中扩散。逻辑电路由由P型第二区域，第一N型区域和P型隔离区域构成的第一垂直PNP晶体管和由第一N型区域形成的第二垂直NPN晶体管构成，P型隔离区域和N型埋设地区。

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