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1. 发明授权

US06690220B2 Reset circuit of semiconductor circuit 失效
标题翻译：半导体电路复位电路
公开(公告)号：US06690220B2
公开(公告)日：2004-02-10
申请号：US09894840
申请日：2001-06-29
申请人： Masanobu Kuboshima , Keisuke Tanaka , Toshihiko Maruoka
发明人： Masanobu Kuboshima , Keisuke Tanaka , Toshihiko Maruoka
IPC分类号： H03K302
CPC分类号： H03K17/18 , H03K17/22
摘要： A reset circuit of a semiconductor circuit for reliably resetting plural reset target circuits in the semiconductor circuit, even when a surge noise signal having a short pulse length or the like is input to the reset circuit, the reset circuit including a reset signal control circuit for controlling timing of deactivating a reset instruction signal for resetting plural reset target circuits in the semiconductor circuit. Respective reset target circuits are for outputting reset completion signals to the reset signal control circuit when the respective reset target circuits have been reset. The reset signal control circuit also is for deactivating the reset instruction signal when all of the reset completion signals have been activated.
摘要翻译：即使当具有短脉冲长度等的浪涌噪声信号被输入到复位电路时，半导体电路的复位电路可靠地复位半导体电路中的多个复位目标电路，复位电路包括一个复位信号控制电路控制用于复位半导体电路中的多个复位目标电路的复位指令信号的定时。各复位目标电路用于在复位目标电路复位时将复位完成信号输出到复位信号控制电路。复位信号控制电路也用于当所有复位完成信号都被激活时，使复位指令信号无效。

2. 发明申请

US20050240701A1 Interrupt control apparatus 审中-公开
标题翻译：中断控制装置
公开(公告)号：US20050240701A1
公开(公告)日：2005-10-27
申请号：US11115270
申请日：2005-04-27
申请人： Masanobu Kuboshima , Toshiya Kai
发明人： Masanobu Kuboshima , Toshiya Kai
IPC分类号： G06F9/48 , G06F9/46 , G06F13/24 , G06F13/26
CPC分类号： G06F13/24
摘要： Apparatus for controlling multiple interrupts comprises units for: pre-storing, for each interrupt cause, information identifying an interrupt processing program executed in response to occurrence of the interrupt cause and level information indicating the interrupt processing program level; comparing, upon occurrence of an interrupt cause, execution levels indicated by the level information and by an intra-CPU processor status word; saving, into an inside-memory stack area, CPU information including the processor status word and the program counter content in CPU; reading the CPU information from the stack area and restoring it into the CPU; performing control for, if the comparison result shows the level-information execution level is no lower than the processor-status-word level, having the saving unit save the CPU information before executing the corresponding interrupt processing program at a corresponding level, and having the restoration unit restore the CPU information after the interrupt processing program finishes being executed.
摘要翻译：用于控制多个中断的装置包括以下单元：用于每个中断原因预先存储识别响应于中断原因的发生而执行的中断处理程序的信息和指示中断处理程序级的电平信息; 在发生中断原因时，比较由电平信息和内部CPU处理器状态字指示的执行电平; 保存到内部存储器堆栈区域中，CPU信息包括CPU中的处理器状态字和程序计数器内容; 从堆栈区读取CPU信息并将其还原到CPU中; 执行控制，如果比较结果显示电平信息执行级别不低于处理器状态字电平，则在执行相应级别的相应中断处理程序之前，保存单元保存CPU信息，并且具有中断处理程序执行完毕后，恢复单元恢复CPU信息。

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