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1. 发明授权

US08507998B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08507998B2
公开(公告)日：2013-08-13
申请号：US13408101
申请日：2012-02-29
申请人： Masaharu Yamaji , Akio Kitamura
发明人： Masaharu Yamaji , Akio Kitamura
IPC分类号： H01L29/76
CPC分类号： H01L27/0883
摘要： A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.
摘要翻译：半导体器件可以输出用于任意电位的参考电压，并且可以非常精确地检测包括多个单元的电池中的每个单元的电压。该器件包括耗尽型MOSFET21和增强型MOSFET22，并且具有从耗尽型MOSFET21和增强型MOSFET22与接地端子隔离的浮置结构。耗尽型MOSFET21和增强型MOSFET22彼此串联连接，其中耗尽型MOSFET21连接到高电位侧端子，增强型MOSFET22连接到低电位侧端子。具有上述结构的半导体器件设置在包括多个单元的电池的控制IC中的电压检测电路部分中。

2. 发明申请

US20130001736A1 HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：高电压集成电路设备
公开(公告)号：US20130001736A1
公开(公告)日：2013-01-03
申请号：US13515546
申请日：2011-09-12
申请人： Masaharu Yamaji
发明人： Masaharu Yamaji
IPC分类号： H01L23/48
CPC分类号： H01L21/823481 , H01L21/823493 , H01L27/0203 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage integrated circuit device has formed therein a high-voltage junction terminating region that is configured by a breakdown voltage region formed of an n-well region, a ground potential region formed of a p-region, a first contact region and a second contact region. An opposition section of the high-voltage junction terminating region, whose distance to an intermediate-potential region formed of a p-drain region is shorter than those of other sections, is provided with a resistance higher than those of the other sections. Accordingly, a cathode resistance of a parasitic diode formed of the p-region and the n-well region increases, locally reducing the amount of electron holes injected at the time of the input of a negative-voltage surge. As a result, an erroneous operation or destruction of a logic part of a high-side circuit can be prevented when the negative-voltage surge is applied to an H-VDD terminal or a Vs terminal.
摘要翻译：一种高电压集成电路器件，其中形成有由n-阱区形成的击穿电压区域，由p区形成的接地电位区域，第一接触区域和第二接触区域。与p型漏极区域形成的中间电位区域的距离比其他部分短的高压结终止区域的对置部分具有比其他部分高的电阻。因此，由p区域和n阱区域形成的寄生二极管的阴极电阻增加，从而局部地减少在输入负电压浪涌时注入的电子空穴量。结果，当向H-VDD端子或Vs端子施加负电压浪涌时，可以防止高侧电路的逻辑部分的错误操作或破坏。

3. 发明申请

US20110133269A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20110133269A1
公开(公告)日：2011-06-09
申请号：US12917719
申请日：2010-11-02
申请人： Masaharu YAMAJI
发明人： Masaharu YAMAJI
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/41758 , H01L29/7824 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes, below a high-voltage wiring, a p− diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p− diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.
摘要翻译：半导体装置包括在高电压布线下面，与n漏极缓冲层接触的扩散层和与扩散层接触的p +扩散层，用于降低绝缘膜中的电场强度，其中高电压接线越过。降低绝缘膜中的电场强度可防止高压NMOSFET的击穿电压降低，层间绝缘膜的分解，以及器件隔离沟槽的隔离击穿电压的损害。根据本发明的半导体装置有助于从高压NMOSFET和这种电平移位装置将高电压布线桥接到跨越器件隔离沟槽的高电压浮动区，而不会损害高电压的击穿电压 NMOSFET，而不会破坏层间绝缘膜，而不损害器件隔离沟槽的隔离击穿电压。

4. 发明申请

US20100314710A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE 有权
标题翻译：高压半导体器件
公开(公告)号：US20100314710A1
公开(公告)日：2010-12-16
申请号：US12813178
申请日：2010-06-10
申请人： Masaharu YAMAJI
发明人： Masaharu YAMAJI
IPC分类号： H01L27/06
CPC分类号： H01L27/088 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/1203 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/405 , H01L29/42368 , H01L29/4238 , H01L29/7817 , H01L29/7821 , H01L29/7824 , H01L2224/02166 , H01L2224/04042 , H01L2224/05552 , H01L2224/05599 , H01L2224/45124 , H01L2224/48091 , H01L2224/4813 , H01L2224/48464 , H01L2224/48699 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01031 , H01L2924/01033 , H01L2924/01082 , H01L2924/05042 , H01L2924/12035 , H01L2924/12036 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad.
摘要翻译：本发明的方面提供高压半导体器件和高压集成电路器件，同时最小化或消除了对后表面步骤的添加的需要。本发明提供一种通过稳定的高压布线和低导通电压实现低电压驱动和快速响应的高压半导体器件。在本发明的一些方面中，高电压半导体器件可以包括在支撑衬底上形成半导体层，所述衬底在其间插入嵌入的氧化膜。围绕第二级晶体管的高电位侧第二级晶体管和低电位侧第一级晶体管形成在半导体层的表面区域上。第二级晶体管的源电极连接到第一级晶体管的漏电极。第二级晶体管的漏电极连接到漏极焊盘。

5. 发明授权

US08674729B2 High voltage semiconductor device and driving circuit 有权
标题翻译：高压半导体器件和驱动电路
公开(公告)号：US08674729B2
公开(公告)日：2014-03-18
申请号：US13256222
申请日：2010-09-29
申请人： Masaharu Yamaji
发明人： Masaharu Yamaji
IPC分类号： H03K3/00
CPC分类号： H01L29/7816 , H01L24/05 , H01L29/0646 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L2224/02166 , H01L2224/04042 , H01L2224/05552 , H01L2224/48091 , H01L2924/12036 , H01L2924/1301 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H03K17/567 , H03K17/6871 , H03K2217/0063 , H03K2217/0081 , H01L2924/00014 , H01L2924/00
摘要： A high voltage semiconductor device is provided and includes an n−-type region encompassed by a p− well region and is provided on a p−-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p−-region is provided that passes through the n−-type region to the silicon substrate. The n−-type region is divided, by the p−-region, into a drift n−-type region having the drain n+-region and a floating n−-type region having a floating electric potential.
摘要翻译：提供了高压半导体器件，并且包括由p阱区域包围的n型区域，并且设置在p型硅衬底上。漏极n +区域连接到漏电极。形成p基区以便与漏极n +区分离并包围漏极n +区。在p基区形成源n +区。此外，提供了通过n型区域到硅衬底的p区。 n型区域由p区域划分成具有漏极n +区域的漂移n型区域和具有浮置电位的浮置n型区域。

6. 发明申请

US20120235712A1 HIGH VOLTAGE SEMICONDUCTOR DEVICE AND DRIVING CIRCUIT 有权
标题翻译：高电压半导体器件和驱动电路
公开(公告)号：US20120235712A1
公开(公告)日：2012-09-20
申请号：US13256222
申请日：2010-09-29
申请人： Masaharu Yamaji
发明人： Masaharu Yamaji
IPC分类号： H01L27/092 , H03K3/00
CPC分类号： H01L29/7816 , H01L24/05 , H01L29/0646 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L2224/02166 , H01L2224/04042 , H01L2224/05552 , H01L2224/48091 , H01L2924/12036 , H01L2924/1301 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H03K17/567 , H03K17/6871 , H03K2217/0063 , H03K2217/0081 , H01L2924/00014 , H01L2924/00
摘要： A high voltage semiconductor device is provided and includes an n−-type region encompassed by a p− well region and is provided on a p−-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p−-region is provided that passes through the n−-type region to the silicon substrate. The n−-type region is divided, by the p−-region, into a drift n−-type region having the drain n+-region and a floating n−-type region having a floating electric potential.
摘要翻译：提供了高压半导体器件，并且包括由p阱区域包围的n型区域，并且设置在p型硅衬底上。漏极n +区域连接到漏电极。形成p基区以便与漏极n +区分离并包围漏极n +区。在p基区形成源n +区。此外，提供了通过n型区域到硅衬底的p区。 n型区域由p区域划分成具有漏极n +区域的漂移n型区域和具有浮置电位的浮置n型区域。

7. 发明授权

US08242572B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08242572B2
公开(公告)日：2012-08-14
申请号：US12917719
申请日：2010-11-02
申请人： Masaharu Yamaji
发明人： Masaharu Yamaji
IPC分类号： H01L23/58
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/41758 , H01L29/7824 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes, below a high-voltage wiring, a p− diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p− diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.
摘要翻译：半导体装置包括在高电压布线下面，与n漏极缓冲层接触的扩散层和与扩散层接触的p +扩散层，用于降低绝缘膜中的电场强度，其中高电压接线越过。降低绝缘膜中的电场强度可防止高压NMOSFET的击穿电压降低，层间绝缘膜的分解，以及器件隔离沟槽的隔离击穿电压的损害。根据本发明的半导体装置有助于从高压NMOSFET和这种电平移位装置将高电压布线桥接到跨越器件隔离沟槽的高电压浮动区，而不会损害高电压的击穿电压 NMOSFET，而不会破坏层间绝缘膜，而不损害器件隔离沟槽的隔离击穿电压。

8. 发明申请

US20100264491A1 HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE AND HIGH VOLTAGE INTEGRATED CIRCUIT 有权
标题翻译：高电压半导体器件和高电压集成电路
公开(公告)号：US20100264491A1
公开(公告)日：2010-10-21
申请号：US12719541
申请日：2010-03-08
申请人： Masaharu YAMAJI
发明人： Masaharu YAMAJI
IPC分类号： H01L29/78 , H01L29/861
CPC分类号： H01L29/0696 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L29/0619 , H01L29/0878 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/7824 , H01L2224/02166 , H01L2224/04042 , H01L2224/05555 , H01L2224/05599 , H01L2224/45124 , H01L2224/48091 , H01L2224/4813 , H01L2224/48463 , H01L2224/48699 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/05042 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H02M3/28 , H01L2924/00
摘要： A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer 113 and buffer layer is a non-continuous or continuous ring.
摘要翻译：在半导体衬底上跨越电介质层形成半导体层的高耐压电压半导体器件包括在半导体层上的漏极层，形成为包围漏极层的缓冲层，源极层所述漏极层形成为围绕其周围，形成为包围所述源极层的阱层以及形成在所述半导体层上的栅极绝缘膜之间的栅电极，其中，所述漏极层113的平面形状并且缓冲层是非连续或连续的环。

9. 发明申请

US20090072867A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090072867A1
公开(公告)日：2009-03-19
申请号：US12210775
申请日：2008-09-15
申请人： Masaharu YAMAJI , Akio KITAMURA
发明人： Masaharu YAMAJI , Akio KITAMURA
IPC分类号： G05F1/10 , H01L27/088
CPC分类号： H01L27/0883
摘要： A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.
摘要翻译：半导体器件可以输出用于任意电位的参考电压，并且可以非常精确地检测包括多个单元的电池中的每个单元的电压。该器件包括耗尽型MOSFET21和增强型MOSFET22，并且具有从耗尽型MOSFET21和增强型MOSFET22与接地端子隔离的浮置结构。耗尽型MOSFET21和增强型MOSFET22彼此串联连接，其中耗尽型MOSFET21连接到高电位侧端子，增强型MOSFET22连接到低电位侧端子。具有上述结构的半导体器件设置在包括多个单元的电池的控制IC中的电压检测电路部分中。

10. 发明授权

US08841744B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08841744B2
公开(公告)日：2014-09-23
申请号：US13448739
申请日：2012-04-17
申请人： Tomohiro Imai , Masaharu Yamaji
发明人： Tomohiro Imai , Masaharu Yamaji
IPC分类号： H01L23/58
CPC分类号： H01L27/0248 , H01L21/823892 , H01L27/0922 , H01L29/0646 , H01L29/0649 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n− epitaxial layer between a bootstrap diode Db and a p-type GND region at the ground potential (GND). The p-type floating region extends to the cavity for suppressing the leakage current caused by the holes flowing to the p− substrate in charging an externally attached bootstrap capacitor C1. The semiconductor apparatus which includes a bootstrap-type driver circuit facilitates suppressing the leakage current caused by the holes flowing to the p− substrate, when the bootstrap diode is biased in forward.
摘要翻译：具有自举型驱动器电路的半导体装置包括形成在自举二极管Db下面的SON结构的空腔和形成在自举二极管Db和p型GND区域之间的外延层中的p型浮动区域地电位（GND）。 p型浮动区域延伸到空腔，用于在对外部附接的自举电容器C1充电时抑制由流向p基板的孔引起的漏电流。包括自举型驱动电路的半导体装置有助于抑制当自举二极管向前偏置时，流向p基板的孔所引起的漏电流。

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