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    • 1. 发明授权
    • Load generator used in semiconductor memory device
    • 用于半导体存储器件的负载发生器
    • US5453956A
    • 1995-09-26
    • US382408
    • 1995-02-01
    • Akihiro IwaseTeruo SekiMasaharu Kagohashi
    • Akihiro IwaseTeruo SekiMasaharu Kagohashi
    • G11C11/419G11C7/10G11C11/409G11C11/413H03K5/02G11C11/40G11C13/00
    • G11C7/1048
    • A load generator is disclosed, which controls the voltage swing of the complementary logic signals generated in a semiconductor memory device. The load generator includes a first load circuit for controlling the potential levels of the signals appearing on a pair of complementary input signal lines. The first load circuit includes a first and second voltage dividers connected to the complementary input signal lines. Each of the first and second voltage dividers include a first voltage dividing transistor and a first voltage dividing resistive element connected in series between the semiconductor's low and high potential power supplies. The two first voltage dividing transistors are connected to each other in such a manner that a voltage, divided by one of the two transistors, is applied to the gate of the other transistor. The load generator further includes a second load circuit for controlling the potential levels of the signals appearing on a pair of complementary output signal lines. The second load circuit includes a third and fourth voltage dividing circuits associated with the first and second voltage dividing circuits and connected to the complementary output signal lines, respectively. Each of the third and fourth voltage dividing circuits includes a second voltage dividing transistor and a second voltage dividing resistive element, connected in series between the low and high potential power supplies.
    • 公开了一种负载发生器,其控制在半导体存储器件中产生的互补逻辑信号的电压摆幅。 负载发生器包括用于控制出现在一对互补输入信号线上的信号的电位电平的第一负载电路。 第一负载电路包括连接到互补输入信号线的第一和第二分压器。 第一和第二分压器中的每一个包括串联连接在半导体的低电位和高电位电源之间的第一分压晶体管和第一分压电阻元件。 两个第一分压晶体管彼此连接,使得由两个晶体管中的一个分压的电压施加到另一个晶体管的栅极。 负载发生器还包括用于控制出现在一对互补输出信号线上的信号的电位电平的第二负载电路。 第二负载电路包括与第一和第二分压电路相关联并分别连接到互补输出信号线的第三和第四分压电路。 第三和第四分压电路中的每一个包括串联连接在低电位和高电位电源之间的第二分压晶体管和第二分压电阻元件。
    • 2. 发明授权
    • Data outputting circuit for semiconductor memory device
    • 半导体存储器件的数据输出电路
    • US5631865A
    • 1997-05-20
    • US562745
    • 1995-11-27
    • Akihiro IwaseMasaharu Kagohashi
    • Akihiro IwaseMasaharu Kagohashi
    • G11C11/419G11C7/10G11C11/409G11C7/00
    • G11C7/1048
    • A semiconductor memory device includes a sense amplifier and a load circuit which are connected to a pair of data buses through which cell data is read. The sense amplifier produces an output data signal in accordance with voltage potentials of transfer signals on the data buses. During data reading operation of the memory device, the sense amplifier is enabled and the transfer signals on the data buses have a different voltage potential level from each other. The load circuit sets the data buses at a predetermined reset voltage potential in a stand by state of the data reading operation. The reset voltage potential is intermediate of the voltage potential levels of the data buses when the sense amplifier is enabled.
    • 半导体存储器件包括读出放大器和负载电路,其连接到读取单元数据的一对数据总线。 读出放大器根据数据总线上传输信号的电压电位产生输出数据信号。 在存储器件的数据读取操作期间,读出放大器被使能,数据总线上的传输信号彼此之间具有不同的电压电位。 负载电路通过数据读取操作的状态将数据总线设置在待机状态下的预定复位电压电位。 当启用读出放大器时,复位电压电位是数据总线的电压电位电平的中间。